1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> 5 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> 6 * 7 * Product homepage: 8 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ 9 */ 10 11#include <dt-bindings/leds/common.h> 12 13#include "imx93.dtsi" 14 15/{ 16 model = "PHYTEC phyCORE-i.MX93"; 17 compatible = "phytec,imx93-phycore-som", "fsl,imx93"; 18 19 aliases { 20 ethernet0 = &fec; 21 }; 22 23 reserved-memory { 24 ranges; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 linux,cma { 29 compatible = "shared-dma-pool"; 30 reusable; 31 alloc-ranges = <0 0x80000000 0 0x40000000>; 32 size = <0 0x10000000>; 33 linux,cma-default; 34 }; 35 }; 36 37 leds { 38 compatible = "gpio-leds"; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&pinctrl_leds>; 41 42 led-0 { 43 color = <LED_COLOR_ID_GREEN>; 44 function = LED_FUNCTION_HEARTBEAT; 45 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 46 linux,default-trigger = "heartbeat"; 47 }; 48 }; 49 50 reg_vdda_1v8: regulator-vdda-1v8 { 51 compatible = "regulator-fixed"; 52 regulator-name = "VDDA_1V8"; 53 regulator-min-microvolt = <1800000>; 54 regulator-max-microvolt = <1800000>; 55 vin-supply = <&buck5>; 56 }; 57}; 58 59/* ADC */ 60&adc1 { 61 vref-supply = <®_vdda_1v8>; 62}; 63 64/* Ethernet */ 65&fec { 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_fec>; 68 phy-mode = "rmii"; 69 phy-handle = <ðphy1>; 70 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 71 <&clk IMX93_CLK_ENET_REF>, 72 <&clk IMX93_CLK_ENET_REF_PHY>; 73 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 74 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 75 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 76 assigned-clock-rates = <100000000>, <50000000>, <50000000>; 77 status = "okay"; 78 79 mdio: mdio { 80 clock-frequency = <5000000>; 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 ethphy1: ethernet-phy@1 { 85 compatible = "ethernet-phy-ieee802.3-c22"; 86 reg = <1>; 87 reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; 88 reset-assert-us = <30>; 89 }; 90 }; 91}; 92 93/* I2C3 */ 94&lpi2c3 { 95 clock-frequency = <400000>; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_lpi2c3>; 98 status = "okay"; 99 100 pmic@25 { 101 compatible = "nxp,pca9451a"; 102 reg = <0x25>; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_pmic>; 105 interrupt-parent = <&gpio4>; 106 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 107 108 regulators { 109 buck1: BUCK1 { 110 regulator-name = "VDD_SOC"; 111 regulator-min-microvolt = <610000>; 112 regulator-max-microvolt = <950000>; 113 regulator-boot-on; 114 regulator-always-on; 115 regulator-ramp-delay = <3125>; 116 }; 117 118 buck2: BUCK2 { 119 regulator-name = "VDDQ_0V6"; 120 regulator-min-microvolt = <600000>; 121 regulator-max-microvolt = <600000>; 122 regulator-boot-on; 123 regulator-always-on; 124 }; 125 126 buck4: BUCK4 { 127 regulator-name = "VDD_3V3_BUCK"; 128 regulator-min-microvolt = <3300000>; 129 regulator-max-microvolt = <3300000>; 130 regulator-boot-on; 131 regulator-always-on; 132 }; 133 134 buck5: BUCK5 { 135 regulator-name = "VDD_1V8"; 136 regulator-min-microvolt = <1800000>; 137 regulator-max-microvolt = <1800000>; 138 regulator-boot-on; 139 regulator-always-on; 140 }; 141 142 buck6: BUCK6 { 143 regulator-name = "VDD_1V1"; 144 regulator-min-microvolt = <1100000>; 145 regulator-max-microvolt = <1100000>; 146 regulator-boot-on; 147 regulator-always-on; 148 }; 149 150 ldo1: LDO1 { 151 regulator-name = "PMIC_SNVS_1V8"; 152 regulator-min-microvolt = <1800000>; 153 regulator-max-microvolt = <1800000>; 154 regulator-boot-on; 155 regulator-always-on; 156 }; 157 158 ldo4: LDO4 { 159 regulator-name = "VDD_0V8"; 160 regulator-min-microvolt = <800000>; 161 regulator-max-microvolt = <800000>; 162 regulator-boot-on; 163 regulator-always-on; 164 }; 165 166 ldo5: LDO5 { 167 regulator-name = "NVCC_SD2"; 168 regulator-min-microvolt = <1800000>; 169 regulator-max-microvolt = <3300000>; 170 regulator-boot-on; 171 regulator-always-on; 172 }; 173 }; 174 }; 175 176 /* EEPROM */ 177 eeprom@50 { 178 compatible = "atmel,24c32"; 179 reg = <0x50>; 180 pagesize = <32>; 181 vcc-supply = <&buck4>; 182 }; 183}; 184 185/* eMMC */ 186&usdhc1 { 187 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 188 pinctrl-0 = <&pinctrl_usdhc1>; 189 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 190 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 191 bus-width = <8>; 192 non-removable; 193 no-1-8-v; 194 status = "okay"; 195}; 196 197/* Watchdog */ 198&wdog3 { 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_wdog>; 201 fsl,ext-reset-output; 202 status = "okay"; 203}; 204 205&iomuxc { 206 pinctrl_fec: fecgrp { 207 fsl,pins = < 208 MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e 209 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 210 /* the three pins below are connected to PHYs straps, 211 * that is what the pull-up/down setting is for. 212 */ 213 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x37e 214 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x37e 215 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 216 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e 217 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e 218 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e 219 MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e 220 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 221 >; 222 }; 223 224 pinctrl_leds: ledsgrp { 225 fsl,pins = < 226 MX93_PAD_I2C1_SDA__GPIO1_IO01 0x11e 227 >; 228 }; 229 230 pinctrl_lpi2c3: lpi2c3grp { 231 fsl,pins = < 232 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 233 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 234 >; 235 }; 236 237 pinctrl_pmic: pmicgrp { 238 fsl,pins = < 239 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e 240 >; 241 }; 242 243 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 244 pinctrl_usdhc1: usdhc1grp { 245 fsl,pins = < 246 MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e 247 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 248 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 249 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 250 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 251 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 252 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 253 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 254 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 255 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 256 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e 257 >; 258 }; 259 260 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 261 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 262 fsl,pins = < 263 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be 264 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e 265 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 266 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e 267 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be 268 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e 269 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e 270 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e 271 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e 272 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e 273 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e 274 >; 275 }; 276 277 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 278 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 279 fsl,pins = < 280 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be 281 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e 282 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e 283 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be 284 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be 285 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be 286 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be 287 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be 288 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be 289 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be 290 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e 291 >; 292 }; 293 294 pinctrl_wdog: wdoggrp { 295 fsl,pins = < 296 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 297 >; 298 }; 299}; 300