1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> 5 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> 6 * 7 * Product homepage: 8 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ 9 */ 10 11#include <dt-bindings/leds/common.h> 12 13#include "imx93.dtsi" 14 15/{ 16 model = "PHYTEC phyCORE-i.MX93"; 17 compatible = "phytec,imx93-phycore-som", "fsl,imx93"; 18 19 aliases { 20 ethernet0 = &fec; 21 }; 22 23 reserved-memory { 24 ranges; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 linux,cma { 29 compatible = "shared-dma-pool"; 30 reusable; 31 alloc-ranges = <0 0x80000000 0 0x40000000>; 32 size = <0 0x10000000>; 33 linux,cma-default; 34 }; 35 }; 36 37 leds { 38 compatible = "gpio-leds"; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&pinctrl_leds>; 41 42 led-0 { 43 color = <LED_COLOR_ID_GREEN>; 44 function = LED_FUNCTION_HEARTBEAT; 45 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 46 linux,default-trigger = "heartbeat"; 47 }; 48 }; 49 50 reg_vdda_1v8: regulator-vdda-1v8 { 51 compatible = "regulator-fixed"; 52 regulator-name = "VDDA_1V8"; 53 regulator-min-microvolt = <1800000>; 54 regulator-max-microvolt = <1800000>; 55 vin-supply = <&buck5>; 56 }; 57}; 58 59/* ADC */ 60&adc1 { 61 vref-supply = <®_vdda_1v8>; 62}; 63 64/* Ethernet */ 65&fec { 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_fec>; 68 phy-mode = "rmii"; 69 phy-handle = <ðphy1>; 70 fsl,magic-packet; 71 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 72 <&clk IMX93_CLK_ENET_REF>, 73 <&clk IMX93_CLK_ENET_REF_PHY>; 74 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 75 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 76 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 77 assigned-clock-rates = <100000000>, <50000000>, <50000000>; 78 status = "okay"; 79 80 mdio: mdio { 81 clock-frequency = <5000000>; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 ethphy1: ethernet-phy@1 { 86 compatible = "ethernet-phy-ieee802.3-c22"; 87 reg = <1>; 88 }; 89 }; 90}; 91 92/* I2C3 */ 93&lpi2c3 { 94 clock-frequency = <400000>; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_lpi2c3>; 97 status = "okay"; 98 99 pmic@25 { 100 compatible = "nxp,pca9451a"; 101 reg = <0x25>; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_pmic>; 104 interrupt-parent = <&gpio4>; 105 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 106 107 regulators { 108 buck1: BUCK1 { 109 regulator-name = "VDD_SOC"; 110 regulator-min-microvolt = <610000>; 111 regulator-max-microvolt = <950000>; 112 regulator-boot-on; 113 regulator-always-on; 114 regulator-ramp-delay = <3125>; 115 }; 116 117 buck2: BUCK2 { 118 regulator-name = "VDDQ_0V6"; 119 regulator-min-microvolt = <600000>; 120 regulator-max-microvolt = <600000>; 121 regulator-boot-on; 122 regulator-always-on; 123 }; 124 125 buck4: BUCK4 { 126 regulator-name = "VDD_3V3_BUCK"; 127 regulator-min-microvolt = <3300000>; 128 regulator-max-microvolt = <3300000>; 129 regulator-boot-on; 130 regulator-always-on; 131 }; 132 133 buck5: BUCK5 { 134 regulator-name = "VDD_1V8"; 135 regulator-min-microvolt = <1800000>; 136 regulator-max-microvolt = <1800000>; 137 regulator-boot-on; 138 regulator-always-on; 139 }; 140 141 buck6: BUCK6 { 142 regulator-name = "VDD_1V1"; 143 regulator-min-microvolt = <1100000>; 144 regulator-max-microvolt = <1100000>; 145 regulator-boot-on; 146 regulator-always-on; 147 }; 148 149 ldo1: LDO1 { 150 regulator-name = "PMIC_SNVS_1V8"; 151 regulator-min-microvolt = <1800000>; 152 regulator-max-microvolt = <1800000>; 153 regulator-boot-on; 154 regulator-always-on; 155 }; 156 157 ldo4: LDO4 { 158 regulator-name = "VDD_0V8"; 159 regulator-min-microvolt = <800000>; 160 regulator-max-microvolt = <800000>; 161 regulator-boot-on; 162 regulator-always-on; 163 }; 164 165 ldo5: LDO5 { 166 regulator-name = "NVCC_SD2"; 167 regulator-min-microvolt = <1800000>; 168 regulator-max-microvolt = <3300000>; 169 regulator-boot-on; 170 regulator-always-on; 171 }; 172 }; 173 }; 174 175 /* EEPROM */ 176 eeprom@50 { 177 compatible = "atmel,24c32"; 178 reg = <0x50>; 179 pagesize = <32>; 180 vcc-supply = <&buck4>; 181 }; 182}; 183 184/* eMMC */ 185&usdhc1 { 186 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 187 pinctrl-0 = <&pinctrl_usdhc1>; 188 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 189 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 190 bus-width = <8>; 191 non-removable; 192 no-1-8-v; 193 status = "okay"; 194}; 195 196/* Watchdog */ 197&wdog3 { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_wdog>; 200 fsl,ext-reset-output; 201 status = "okay"; 202}; 203 204&iomuxc { 205 pinctrl_fec: fecgrp { 206 fsl,pins = < 207 MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e 208 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 209 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 210 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 211 MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe 212 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 213 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e 214 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e 215 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e 216 MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e 217 >; 218 }; 219 220 pinctrl_leds: ledsgrp { 221 fsl,pins = < 222 MX93_PAD_I2C1_SDA__GPIO1_IO01 0x11e 223 >; 224 }; 225 226 pinctrl_lpi2c3: lpi2c3grp { 227 fsl,pins = < 228 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 229 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 230 >; 231 }; 232 233 pinctrl_pmic: pmicgrp { 234 fsl,pins = < 235 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e 236 >; 237 }; 238 239 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 240 pinctrl_usdhc1: usdhc1grp { 241 fsl,pins = < 242 MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e 243 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 244 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 245 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 246 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 247 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 248 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 249 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 250 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 251 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 252 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e 253 >; 254 }; 255 256 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 257 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 258 fsl,pins = < 259 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be 260 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e 261 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 262 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e 263 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be 264 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e 265 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e 266 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e 267 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e 268 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e 269 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e 270 >; 271 }; 272 273 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 274 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 275 fsl,pins = < 276 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be 277 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e 278 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e 279 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be 280 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be 281 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be 282 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be 283 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be 284 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be 285 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be 286 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e 287 >; 288 }; 289 290 pinctrl_wdog: wdoggrp { 291 fsl,pins = < 292 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 293 >; 294 }; 295}; 296