1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> 5 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> 6 * 7 * Product homepage: 8 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ 9 */ 10 11#include <dt-bindings/leds/common.h> 12 13#include "imx93.dtsi" 14 15/{ 16 model = "PHYTEC phyCORE-i.MX93"; 17 compatible = "phytec,imx93-phycore-som", "fsl,imx93"; 18 19 reserved-memory { 20 ranges; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 linux,cma { 25 compatible = "shared-dma-pool"; 26 reusable; 27 alloc-ranges = <0 0x80000000 0 0x40000000>; 28 size = <0 0x10000000>; 29 linux,cma-default; 30 }; 31 }; 32 33 leds { 34 compatible = "gpio-leds"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_leds>; 37 38 led-0 { 39 color = <LED_COLOR_ID_GREEN>; 40 function = LED_FUNCTION_HEARTBEAT; 41 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 42 linux,default-trigger = "heartbeat"; 43 }; 44 }; 45}; 46 47/* Ethernet */ 48&fec { 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_fec>; 51 phy-mode = "rmii"; 52 phy-handle = <ðphy1>; 53 fsl,magic-packet; 54 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 55 <&clk IMX93_CLK_ENET_REF>, 56 <&clk IMX93_CLK_ENET_REF_PHY>; 57 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 58 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 59 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 60 assigned-clock-rates = <100000000>, <50000000>, <50000000>; 61 status = "okay"; 62 63 mdio: mdio { 64 clock-frequency = <5000000>; 65 #address-cells = <1>; 66 #size-cells = <0>; 67 68 ethphy1: ethernet-phy@1 { 69 compatible = "ethernet-phy-ieee802.3-c22"; 70 reg = <1>; 71 }; 72 }; 73}; 74 75/* I2C3 */ 76&lpi2c3 { 77 clock-frequency = <400000>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_lpi2c3>; 80 status = "okay"; 81 82 pmic@25 { 83 compatible = "nxp,pca9451a"; 84 reg = <0x25>; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_pmic>; 87 interrupt-parent = <&gpio4>; 88 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 89 90 regulators { 91 buck1: BUCK1 { 92 regulator-name = "VDD_SOC"; 93 regulator-min-microvolt = <610000>; 94 regulator-max-microvolt = <950000>; 95 regulator-boot-on; 96 regulator-always-on; 97 regulator-ramp-delay = <3125>; 98 }; 99 100 buck2: BUCK2 { 101 regulator-name = "VDDQ_0V6"; 102 regulator-min-microvolt = <600000>; 103 regulator-max-microvolt = <600000>; 104 regulator-boot-on; 105 regulator-always-on; 106 }; 107 108 buck4: BUCK4 { 109 regulator-name = "VDD_3V3_BUCK"; 110 regulator-min-microvolt = <3300000>; 111 regulator-max-microvolt = <3300000>; 112 regulator-boot-on; 113 regulator-always-on; 114 }; 115 116 buck5: BUCK5 { 117 regulator-name = "VDD_1V8"; 118 regulator-min-microvolt = <1800000>; 119 regulator-max-microvolt = <1800000>; 120 regulator-boot-on; 121 regulator-always-on; 122 }; 123 124 buck6: BUCK6 { 125 regulator-name = "VDD_1V1"; 126 regulator-min-microvolt = <1100000>; 127 regulator-max-microvolt = <1100000>; 128 regulator-boot-on; 129 regulator-always-on; 130 }; 131 132 ldo1: LDO1 { 133 regulator-name = "PMIC_SNVS_1V8"; 134 regulator-min-microvolt = <1800000>; 135 regulator-max-microvolt = <1800000>; 136 regulator-boot-on; 137 regulator-always-on; 138 }; 139 140 ldo4: LDO4 { 141 regulator-name = "VDD_0V8"; 142 regulator-min-microvolt = <800000>; 143 regulator-max-microvolt = <800000>; 144 regulator-boot-on; 145 regulator-always-on; 146 }; 147 148 ldo5: LDO5 { 149 regulator-name = "NVCC_SD2"; 150 regulator-min-microvolt = <1800000>; 151 regulator-max-microvolt = <3300000>; 152 regulator-boot-on; 153 regulator-always-on; 154 }; 155 }; 156 }; 157 158 /* EEPROM */ 159 eeprom@50 { 160 compatible = "atmel,24c32"; 161 reg = <0x50>; 162 pagesize = <32>; 163 vcc-supply = <&buck4>; 164 }; 165}; 166 167/* eMMC */ 168&usdhc1 { 169 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 170 pinctrl-0 = <&pinctrl_usdhc1>; 171 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 172 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 173 bus-width = <8>; 174 non-removable; 175 no-1-8-v; 176 status = "okay"; 177}; 178 179/* Watchdog */ 180&wdog3 { 181 status = "okay"; 182}; 183 184&iomuxc { 185 pinctrl_fec: fecgrp { 186 fsl,pins = < 187 MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e 188 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 189 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 190 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 191 MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe 192 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 193 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e 194 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e 195 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e 196 MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e 197 >; 198 }; 199 200 pinctrl_leds: ledsgrp { 201 fsl,pins = < 202 MX93_PAD_I2C1_SDA__GPIO1_IO01 0x11e 203 >; 204 }; 205 206 pinctrl_lpi2c3: lpi2c3grp { 207 fsl,pins = < 208 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 209 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 210 >; 211 }; 212 213 pinctrl_pmic: pmicgrp { 214 fsl,pins = < 215 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e 216 >; 217 }; 218 219 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 220 pinctrl_usdhc1: usdhc1grp { 221 fsl,pins = < 222 MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e 223 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 224 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 225 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 226 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 227 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 228 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 229 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 230 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 231 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 232 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e 233 >; 234 }; 235 236 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 237 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 238 fsl,pins = < 239 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be 240 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e 241 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 242 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e 243 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be 244 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e 245 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e 246 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e 247 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e 248 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e 249 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e 250 >; 251 }; 252 253 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 254 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 255 fsl,pins = < 256 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be 257 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e 258 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e 259 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be 260 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be 261 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be 262 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be 263 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be 264 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be 265 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be 266 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e 267 >; 268 }; 269}; 270