1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> 5 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> 6 * 7 * Product homepage: 8 * phyBOARD-Segin carrier board is reused for the i.MX93 design. 9 * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ 10 */ 11/dts-v1/; 12 13#include "imx93-phycore-som.dtsi" 14 15/{ 16 model = "PHYTEC phyBOARD-Segin-i.MX93"; 17 compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", 18 "fsl,imx93"; 19 20 aliases { 21 rtc0 = &i2c_rtc; 22 rtc1 = &bbnsm_rtc; 23 }; 24 25 chosen { 26 stdout-path = &lpuart1; 27 }; 28 29 flexcan1_tc: can-phy0 { 30 compatible = "ti,tcan1043"; 31 #phy-cells = <0>; 32 max-bitrate = <1000000>; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_flexcan1_tc>; 35 enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 36 }; 37 38 reg_sound_1v8: regulator-sound-1v8 { 39 compatible = "regulator-fixed"; 40 regulator-max-microvolt = <1800000>; 41 regulator-min-microvolt = <1800000>; 42 regulator-name = "VCC1V8_AUDIO"; 43 }; 44 45 reg_sound_3v3: regulator-sound-3v3 { 46 compatible = "regulator-fixed"; 47 regulator-max-microvolt = <3300000>; 48 regulator-min-microvolt = <3300000>; 49 regulator-name = "VCC3V3_ANALOG"; 50 }; 51 52 reg_usdhc2_vmmc: regulator-usdhc2 { 53 compatible = "regulator-fixed"; 54 enable-active-high; 55 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 regulator-name = "VCC_SD"; 61 }; 62 63 sound: sound { 64 compatible = "simple-audio-card"; 65 simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; 66 simple-audio-card,format = "i2s"; 67 simple-audio-card,bitclock-master = <&dailink_master>; 68 simple-audio-card,frame-master = <&dailink_master>; 69 simple-audio-card,widgets = 70 "Line", "Line In", 71 "Line", "Line Out", 72 "Speaker", "Speaker"; 73 simple-audio-card,routing = 74 "Line Out", "LLOUT", 75 "Line Out", "RLOUT", 76 "Speaker", "SPOP", 77 "Speaker", "SPOM", 78 "LINE1L", "Line In", 79 "LINE1R", "Line In"; 80 81 simple-audio-card,cpu { 82 sound-dai = <&sai1>; 83 }; 84 85 dailink_master: simple-audio-card,codec { 86 sound-dai = <&audio_codec>; 87 clocks = <&clk IMX93_CLK_SAI1>; 88 }; 89 }; 90}; 91 92/* Ethernet */ 93&eqos { 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_eqos>; 96 phy-mode = "rmii"; 97 phy-handle = <ðphy2>; 98 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 99 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 100 assigned-clock-rates = <100000000>, <50000000>; 101 status = "okay"; 102}; 103 104&mdio { 105 ethphy2: ethernet-phy@2 { 106 compatible = "ethernet-phy-id0022.1561"; 107 reg = <2>; 108 clocks = <&clk IMX93_CLK_ENET_REF_PHY>; 109 clock-names = "rmii-ref"; 110 micrel,led-mode = <1>; 111 }; 112}; 113 114/* CAN */ 115&flexcan1 { 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_flexcan1>; 118 phys = <&flexcan1_tc>; 119 status = "okay"; 120}; 121 122/* I2C2 */ 123&lpi2c2 { 124 clock-frequency = <400000>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_lpi2c2>; 127 status = "okay"; 128 129 /* Codec */ 130 audio_codec: audio-codec@18 { 131 compatible = "ti,tlv320aic3007"; 132 reg = <0x18>; 133 #sound-dai-cells = <0>; 134 AVDD-supply = <®_sound_3v3>; 135 IOVDD-supply = <®_sound_3v3>; 136 DRVDD-supply = <®_sound_3v3>; 137 DVDD-supply = <®_sound_1v8>; 138 }; 139 140 /* RTC */ 141 i2c_rtc: rtc@68 { 142 compatible = "microcrystal,rv4162"; 143 reg = <0x68>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_rtc>; 146 interrupt-parent = <&gpio4>; 147 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 148 }; 149}; 150 151/* Console */ 152&lpuart1 { 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_uart1>; 155 status = "okay"; 156}; 157 158/* Audio */ 159&sai1 { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_sai1>; 162 assigned-clocks = <&clk IMX93_CLK_SAI1>; 163 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 164 assigned-clock-rates = <19200000>; 165 fsl,sai-mclk-direction-output; 166 status = "okay"; 167}; 168 169/* USB */ 170&usbotg1 { 171 disable-over-current; 172 dr_mode = "otg"; 173 status = "okay"; 174}; 175 176&usbotg2 { 177 disable-over-current; 178 dr_mode = "host"; 179 status = "okay"; 180}; 181 182/* SD-Card */ 183&usdhc2 { 184 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 185 pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; 186 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 187 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 188 bus-width = <4>; 189 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 190 disable-wp; 191 no-mmc; 192 no-sdio; 193 vmmc-supply = <®_usdhc2_vmmc>; 194 status = "okay"; 195}; 196 197&iomuxc { 198 pinctrl_eqos: eqosgrp { 199 fsl,pins = < 200 MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000050e 201 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 202 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 203 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e 204 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x50e 205 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 206 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e 207 MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e 208 >; 209 }; 210 211 pinctrl_flexcan1: flexcan1grp { 212 fsl,pins = < 213 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 214 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 215 >; 216 }; 217 218 pinctrl_flexcan1_tc: flexcan1tcgrp { 219 fsl,pins = < 220 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e 221 >; 222 }; 223 224 pinctrl_lpi2c2: lpi2c2grp { 225 fsl,pins = < 226 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 227 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 228 >; 229 }; 230 231 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 232 fsl,pins = < 233 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 234 >; 235 }; 236 237 pinctrl_rtc: rtcgrp { 238 fsl,pins = < 239 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e 240 >; 241 }; 242 243 pinctrl_sai1: sai1grp { 244 fsl,pins = < 245 MX93_PAD_UART2_RXD__SAI1_MCLK 0x1202 246 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202 247 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202 248 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x1402 249 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x1402 250 >; 251 }; 252 253 pinctrl_uart1: uart1grp { 254 fsl,pins = < 255 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 256 MX93_PAD_UART1_TXD__LPUART1_TX 0x30e 257 >; 258 }; 259 260 pinctrl_usdhc2_cd: usdhc2cdgrp { 261 fsl,pins = < 262 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 263 >; 264 }; 265 266 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 267 pinctrl_usdhc2_default: usdhc2grp { 268 fsl,pins = < 269 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 270 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 271 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 272 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 273 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 274 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 275 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 276 >; 277 }; 278 279 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 280 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 281 fsl,pins = < 282 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 283 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 284 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 285 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 286 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 287 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 288 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 289 >; 290 }; 291 292 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 293 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 294 fsl,pins = < 295 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 296 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 297 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 298 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 299 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 300 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 301 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 302 >; 303 }; 304}; 305