1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> 5 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> 6 * 7 * Product homepage: 8 * phyBOARD-Segin carrier board is reused for the i.MX93 design. 9 * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ 10 */ 11/dts-v1/; 12 13#include "imx93-phycore-som.dtsi" 14 15/{ 16 model = "PHYTEC phyBOARD-Segin-i.MX93"; 17 compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", 18 "fsl,imx93"; 19 20 chosen { 21 stdout-path = &lpuart1; 22 }; 23 24 reg_usdhc2_vmmc: regulator-usdhc2 { 25 compatible = "regulator-fixed"; 26 enable-active-high; 27 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 30 regulator-min-microvolt = <3300000>; 31 regulator-max-microvolt = <3300000>; 32 regulator-name = "VCC_SD"; 33 }; 34}; 35 36/* Console */ 37&lpuart1 { 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pinctrl_uart1>; 40 status = "okay"; 41}; 42 43/* eMMC */ 44&usdhc1 { 45 no-1-8-v; 46}; 47 48/* SD-Card */ 49&usdhc2 { 50 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 51 pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; 52 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 53 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 54 bus-width = <4>; 55 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 56 no-mmc; 57 no-sdio; 58 vmmc-supply = <®_usdhc2_vmmc>; 59 status = "okay"; 60}; 61 62&iomuxc { 63 pinctrl_uart1: uart1grp { 64 fsl,pins = < 65 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 66 MX93_PAD_UART1_TXD__LPUART1_TX 0x30e 67 >; 68 }; 69 70 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 71 fsl,pins = < 72 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 73 >; 74 }; 75 76 pinctrl_usdhc2_cd: usdhc2cdgrp { 77 fsl,pins = < 78 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 79 >; 80 }; 81 82 pinctrl_usdhc2_default: usdhc2grp { 83 fsl,pins = < 84 MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e 85 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e 86 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 87 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 88 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 89 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e 90 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 91 >; 92 }; 93 94 pinctrl_usdhc2_100mhz: usdhc2grp { 95 fsl,pins = < 96 MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e 97 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e 98 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 99 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 100 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e 101 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e 102 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 103 >; 104 }; 105 106 pinctrl_usdhc2_200mhz: usdhc2grp { 107 fsl,pins = < 108 MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e 109 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e 110 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e 111 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e 112 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e 113 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e 114 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 115 >; 116 }; 117}; 118