1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> 5 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> 6 * 7 * Product homepage: 8 * phyBOARD-Segin carrier board is reused for the i.MX93 design. 9 * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ 10 */ 11/dts-v1/; 12 13#include "imx93-phycore-som.dtsi" 14 15/{ 16 model = "PHYTEC phyBOARD-Segin-i.MX93"; 17 compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", 18 "fsl,imx93"; 19 20 aliases { 21 ethernet1 = &eqos; 22 gpio0 = &gpio1; 23 gpio1 = &gpio2; 24 gpio2 = &gpio3; 25 gpio3 = &gpio4; 26 i2c0 = &lpi2c1; 27 i2c1 = &lpi2c2; 28 mmc0 = &usdhc1; 29 mmc1 = &usdhc2; 30 rtc0 = &i2c_rtc; 31 rtc1 = &bbnsm_rtc; 32 serial0 = &lpuart1; 33 }; 34 35 chosen { 36 stdout-path = &lpuart1; 37 }; 38 39 flexcan1_tc: can-phy0 { 40 compatible = "ti,tcan1043"; 41 #phy-cells = <0>; 42 max-bitrate = <1000000>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_flexcan1_tc>; 45 enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 46 }; 47 48 reg_sound_1v8: regulator-sound-1v8 { 49 compatible = "regulator-fixed"; 50 regulator-max-microvolt = <1800000>; 51 regulator-min-microvolt = <1800000>; 52 regulator-name = "VCC1V8_AUDIO"; 53 }; 54 55 reg_sound_3v3: regulator-sound-3v3 { 56 compatible = "regulator-fixed"; 57 regulator-max-microvolt = <3300000>; 58 regulator-min-microvolt = <3300000>; 59 regulator-name = "VCC3V3_ANALOG"; 60 }; 61 62 reg_usdhc2_vmmc: regulator-usdhc2 { 63 compatible = "regulator-fixed"; 64 enable-active-high; 65 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 68 regulator-min-microvolt = <3300000>; 69 regulator-max-microvolt = <3300000>; 70 regulator-name = "VCC_SD"; 71 }; 72 73 sound: sound { 74 compatible = "simple-audio-card"; 75 simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; 76 simple-audio-card,format = "i2s"; 77 simple-audio-card,bitclock-master = <&dailink_master>; 78 simple-audio-card,frame-master = <&dailink_master>; 79 simple-audio-card,widgets = 80 "Line", "Line In", 81 "Line", "Line Out", 82 "Speaker", "Speaker"; 83 simple-audio-card,routing = 84 "Line Out", "LLOUT", 85 "Line Out", "RLOUT", 86 "Speaker", "SPOP", 87 "Speaker", "SPOM", 88 "LINE1L", "Line In", 89 "LINE1R", "Line In"; 90 91 simple-audio-card,cpu { 92 sound-dai = <&sai1>; 93 }; 94 95 dailink_master: simple-audio-card,codec { 96 sound-dai = <&audio_codec>; 97 clocks = <&clk IMX93_CLK_SAI1>; 98 }; 99 }; 100}; 101 102/* Ethernet */ 103&eqos { 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_eqos>; 106 phy-mode = "rmii"; 107 phy-handle = <ðphy2>; 108 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 109 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 110 assigned-clock-rates = <100000000>, <50000000>; 111 status = "okay"; 112}; 113 114&mdio { 115 ethphy2: ethernet-phy@2 { 116 compatible = "ethernet-phy-id0022.1561"; 117 reg = <2>; 118 clocks = <&clk IMX93_CLK_ENET_REF_PHY>; 119 clock-names = "rmii-ref"; 120 micrel,led-mode = <1>; 121 }; 122}; 123 124/* CAN */ 125&flexcan1 { 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_flexcan1>; 128 phys = <&flexcan1_tc>; 129 status = "okay"; 130}; 131 132/* I2C2 */ 133&lpi2c2 { 134 clock-frequency = <400000>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_lpi2c2>; 137 status = "okay"; 138 139 /* Codec */ 140 audio_codec: audio-codec@18 { 141 compatible = "ti,tlv320aic3007"; 142 reg = <0x18>; 143 #sound-dai-cells = <0>; 144 AVDD-supply = <®_sound_3v3>; 145 IOVDD-supply = <®_sound_3v3>; 146 DRVDD-supply = <®_sound_3v3>; 147 DVDD-supply = <®_sound_1v8>; 148 }; 149 150 /* RTC */ 151 i2c_rtc: rtc@68 { 152 compatible = "microcrystal,rv4162"; 153 reg = <0x68>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_rtc>; 156 interrupt-parent = <&gpio4>; 157 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 158 }; 159}; 160 161/* Console */ 162&lpuart1 { 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_uart1>; 165 status = "okay"; 166}; 167 168/* Audio */ 169&sai1 { 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_sai1>; 172 assigned-clocks = <&clk IMX93_CLK_SAI1>; 173 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 174 assigned-clock-rates = <19200000>; 175 fsl,sai-mclk-direction-output; 176 status = "okay"; 177}; 178 179/* USB */ 180&usbotg1 { 181 disable-over-current; 182 dr_mode = "otg"; 183 status = "okay"; 184}; 185 186&usbotg2 { 187 disable-over-current; 188 dr_mode = "host"; 189 status = "okay"; 190}; 191 192/* SD-Card */ 193&usdhc2 { 194 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 195 pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; 196 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 197 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 198 bus-width = <4>; 199 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 200 disable-wp; 201 no-mmc; 202 no-sdio; 203 vmmc-supply = <®_usdhc2_vmmc>; 204 status = "okay"; 205}; 206 207&iomuxc { 208 pinctrl_eqos: eqosgrp { 209 fsl,pins = < 210 MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000050e 211 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 212 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 213 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e 214 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x50e 215 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 216 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e 217 MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e 218 >; 219 }; 220 221 pinctrl_flexcan1: flexcan1grp { 222 fsl,pins = < 223 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 224 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 225 >; 226 }; 227 228 pinctrl_flexcan1_tc: flexcan1tcgrp { 229 fsl,pins = < 230 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e 231 >; 232 }; 233 234 pinctrl_lpi2c2: lpi2c2grp { 235 fsl,pins = < 236 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 237 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 238 >; 239 }; 240 241 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 242 fsl,pins = < 243 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 244 >; 245 }; 246 247 pinctrl_rtc: rtcgrp { 248 fsl,pins = < 249 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e 250 >; 251 }; 252 253 pinctrl_sai1: sai1grp { 254 fsl,pins = < 255 MX93_PAD_UART2_RXD__SAI1_MCLK 0x1202 256 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202 257 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202 258 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x1402 259 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x1402 260 >; 261 }; 262 263 pinctrl_uart1: uart1grp { 264 fsl,pins = < 265 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 266 MX93_PAD_UART1_TXD__LPUART1_TX 0x30e 267 >; 268 }; 269 270 pinctrl_usdhc2_cd: usdhc2cdgrp { 271 fsl,pins = < 272 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 273 >; 274 }; 275 276 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 277 pinctrl_usdhc2_default: usdhc2grp { 278 fsl,pins = < 279 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 280 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 281 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 282 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 283 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 284 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 285 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 286 >; 287 }; 288 289 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 290 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 291 fsl,pins = < 292 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 293 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 294 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 295 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 296 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 297 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 298 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 299 >; 300 }; 301 302 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 303 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 304 fsl,pins = < 305 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 306 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 307 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 308 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 309 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 310 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 311 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 312 >; 313 }; 314}; 315