1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> 5 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> 6 * 7 * Product homepage: 8 * phyBOARD-Segin carrier board is reused for the i.MX93 design. 9 * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ 10 */ 11/dts-v1/; 12 13#include "imx93-phycore-som.dtsi" 14 15/{ 16 model = "PHYTEC phyBOARD-Segin-i.MX93"; 17 compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", 18 "fsl,imx93"; 19 20 aliases { 21 ethernet1 = &eqos; 22 rtc0 = &i2c_rtc; 23 rtc1 = &bbnsm_rtc; 24 }; 25 26 chosen { 27 stdout-path = &lpuart1; 28 }; 29 30 flexcan1_tc: can-phy0 { 31 compatible = "ti,tcan1043"; 32 #phy-cells = <0>; 33 max-bitrate = <1000000>; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&pinctrl_flexcan1_tc>; 36 enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 37 }; 38 39 reg_sound_1v8: regulator-sound-1v8 { 40 compatible = "regulator-fixed"; 41 regulator-max-microvolt = <1800000>; 42 regulator-min-microvolt = <1800000>; 43 regulator-name = "VCC1V8_AUDIO"; 44 }; 45 46 reg_sound_3v3: regulator-sound-3v3 { 47 compatible = "regulator-fixed"; 48 regulator-max-microvolt = <3300000>; 49 regulator-min-microvolt = <3300000>; 50 regulator-name = "VCC3V3_ANALOG"; 51 }; 52 53 reg_usdhc2_vmmc: regulator-usdhc2 { 54 compatible = "regulator-fixed"; 55 enable-active-high; 56 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 regulator-name = "VCC_SD"; 62 }; 63 64 sound: sound { 65 compatible = "simple-audio-card"; 66 simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; 67 simple-audio-card,format = "i2s"; 68 simple-audio-card,bitclock-master = <&dailink_master>; 69 simple-audio-card,frame-master = <&dailink_master>; 70 simple-audio-card,widgets = 71 "Line", "Line In", 72 "Line", "Line Out", 73 "Speaker", "Speaker"; 74 simple-audio-card,routing = 75 "Line Out", "LLOUT", 76 "Line Out", "RLOUT", 77 "Speaker", "SPOP", 78 "Speaker", "SPOM", 79 "LINE1L", "Line In", 80 "LINE1R", "Line In"; 81 82 simple-audio-card,cpu { 83 sound-dai = <&sai1>; 84 }; 85 86 dailink_master: simple-audio-card,codec { 87 sound-dai = <&audio_codec>; 88 clocks = <&clk IMX93_CLK_SAI1>; 89 }; 90 }; 91}; 92 93/* Ethernet */ 94&eqos { 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_eqos>; 97 phy-mode = "rmii"; 98 phy-handle = <ðphy2>; 99 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 100 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 101 assigned-clock-rates = <100000000>, <50000000>; 102 status = "okay"; 103}; 104 105&mdio { 106 ethphy2: ethernet-phy@2 { 107 compatible = "ethernet-phy-id0022.1561"; 108 reg = <2>; 109 clocks = <&clk IMX93_CLK_ENET_REF_PHY>; 110 clock-names = "rmii-ref"; 111 micrel,led-mode = <1>; 112 }; 113}; 114 115/* CAN */ 116&flexcan1 { 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_flexcan1>; 119 phys = <&flexcan1_tc>; 120 status = "okay"; 121}; 122 123/* I2C2 */ 124&lpi2c2 { 125 clock-frequency = <400000>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_lpi2c2>; 128 status = "okay"; 129 130 /* Codec */ 131 audio_codec: audio-codec@18 { 132 compatible = "ti,tlv320aic3007"; 133 reg = <0x18>; 134 #sound-dai-cells = <0>; 135 AVDD-supply = <®_sound_3v3>; 136 IOVDD-supply = <®_sound_3v3>; 137 DRVDD-supply = <®_sound_3v3>; 138 DVDD-supply = <®_sound_1v8>; 139 }; 140 141 /* RTC */ 142 i2c_rtc: rtc@68 { 143 compatible = "microcrystal,rv4162"; 144 reg = <0x68>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_rtc>; 147 interrupt-parent = <&gpio4>; 148 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 149 }; 150}; 151 152/* Console */ 153&lpuart1 { 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_uart1>; 156 status = "okay"; 157}; 158 159/* Audio */ 160&sai1 { 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_sai1>; 163 assigned-clocks = <&clk IMX93_CLK_SAI1>; 164 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 165 assigned-clock-rates = <19200000>; 166 fsl,sai-mclk-direction-output; 167 status = "okay"; 168}; 169 170/* USB */ 171&usbotg1 { 172 disable-over-current; 173 dr_mode = "otg"; 174 status = "okay"; 175}; 176 177&usbotg2 { 178 disable-over-current; 179 dr_mode = "host"; 180 status = "okay"; 181}; 182 183/* SD-Card */ 184&usdhc2 { 185 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 186 pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; 187 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 188 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 189 bus-width = <4>; 190 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 191 disable-wp; 192 no-mmc; 193 no-sdio; 194 vmmc-supply = <®_usdhc2_vmmc>; 195 status = "okay"; 196}; 197 198&iomuxc { 199 pinctrl_eqos: eqosgrp { 200 fsl,pins = < 201 MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000050e 202 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 203 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 204 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e 205 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x50e 206 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 207 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e 208 MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e 209 >; 210 }; 211 212 pinctrl_flexcan1: flexcan1grp { 213 fsl,pins = < 214 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 215 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 216 >; 217 }; 218 219 pinctrl_flexcan1_tc: flexcan1tcgrp { 220 fsl,pins = < 221 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e 222 >; 223 }; 224 225 pinctrl_lpi2c2: lpi2c2grp { 226 fsl,pins = < 227 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 228 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 229 >; 230 }; 231 232 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 233 fsl,pins = < 234 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 235 >; 236 }; 237 238 pinctrl_rtc: rtcgrp { 239 fsl,pins = < 240 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e 241 >; 242 }; 243 244 pinctrl_sai1: sai1grp { 245 fsl,pins = < 246 MX93_PAD_UART2_RXD__SAI1_MCLK 0x1202 247 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202 248 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202 249 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x1402 250 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x1402 251 >; 252 }; 253 254 pinctrl_uart1: uart1grp { 255 fsl,pins = < 256 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 257 MX93_PAD_UART1_TXD__LPUART1_TX 0x30e 258 >; 259 }; 260 261 pinctrl_usdhc2_cd: usdhc2cdgrp { 262 fsl,pins = < 263 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 264 >; 265 }; 266 267 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 268 pinctrl_usdhc2_default: usdhc2grp { 269 fsl,pins = < 270 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 271 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 272 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 273 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 274 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 275 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 276 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 277 >; 278 }; 279 280 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 281 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 282 fsl,pins = < 283 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 284 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 285 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 286 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 287 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 288 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 289 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 290 >; 291 }; 292 293 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 294 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 295 fsl,pins = < 296 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 297 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 298 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 299 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 300 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 301 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 302 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 303 >; 304 }; 305}; 306