1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 * Author: Primoz Fiser <primoz.fiser@norik.com> 5 * 6 * Product homepage: 7 * https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/ 8 */ 9 10/dts-v1/; 11 12#include <dt-bindings/net/ti-dp83867.h> 13#include "imx93-phycore-som.dtsi" 14 15/ { 16 model = "PHYTEC phyBOARD-Nash-i.MX93"; 17 compatible = "phytec,imx93-phyboard-nash", "phytec,imx93-phycore-som", 18 "fsl,imx93"; 19 20 aliases { 21 ethernet1 = &eqos; 22 rtc0 = &i2c_rtc; 23 rtc1 = &bbnsm_rtc; 24 }; 25 26 chosen { 27 stdout-path = &lpuart1; 28 }; 29 30 flexcan1_tc: can-phy0 { 31 compatible = "ti,tcan1042"; 32 #phy-cells = <0>; 33 max-bitrate = <8000000>; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&pinctrl_flexcan1_tc>; 36 standby-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 37 }; 38 39 reg_usdhc2_vmmc: regulator-usdhc2 { 40 compatible = "regulator-fixed"; 41 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 42 enable-active-high; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 45 regulator-name = "VCC_SD"; 46 regulator-max-microvolt = <3300000>; 47 regulator-min-microvolt = <3300000>; 48 }; 49 50 reg_vcc_1v8: regulator-vcc-1v8 { 51 compatible = "regulator-fixed"; 52 regulator-name = "VCC1V8"; 53 regulator-max-microvolt = <1800000>; 54 regulator-min-microvolt = <1800000>; 55 }; 56}; 57 58/* ADC */ 59&adc1 { 60 status = "okay"; 61}; 62 63/* Ethernet */ 64&eqos { 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_eqos>; 67 phy-mode = "rgmii-id"; 68 phy-handle = <ðphy2>; 69 status = "okay"; 70}; 71 72&mdio { 73 ethphy2: ethernet-phy@2 { 74 compatible = "ethernet-phy-ieee802.3-c22"; 75 reg = <2>; 76 interrupt-parent = <&gpio3>; 77 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 78 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 79 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 80 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>; 81 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 82 }; 83}; 84 85/* CAN */ 86&flexcan1 { 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_flexcan1>; 89 phys = <&flexcan1_tc>; 90 status = "okay"; 91}; 92 93/* I2C2 */ 94&lpi2c2 { 95 clock-frequency = <400000>; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_lpi2c2>; 98 status = "okay"; 99 100 /* RTC */ 101 i2c_rtc: rtc@52 { 102 compatible = "microcrystal,rv3028"; 103 reg = <0x52>; 104 interrupt-parent = <&gpio4>; 105 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_rtc>; 108 trickle-resistor-ohms = <3000>; 109 wakeup-source; 110 }; 111 112 /* EEPROM */ 113 eeprom@54 { 114 compatible = "atmel,24c32"; 115 reg = <0x54>; 116 pagesize = <32>; 117 vcc-supply = <®_vcc_1v8>; 118 }; 119}; 120 121/* SPI6 */ 122&lpspi6 { 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_lpspi6>; 125 cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 126 status = "okay"; 127 128 /* TPM */ 129 tpm@0 { 130 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 131 reg = <0>; 132 interrupt-parent = <&gpio2>; 133 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_tpm>; 136 spi-max-frequency = <10000000>; 137 }; 138}; 139 140/* Console */ 141&lpuart1 { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_uart1>; 144 status = "okay"; 145}; 146 147/* RS-232/RS-485 */ 148&lpuart7 { 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_uart7>; 151 status = "okay"; 152}; 153 154/* USB */ 155&usbotg1 { 156 disable-over-current; 157 dr_mode = "otg"; 158 status = "okay"; 159}; 160 161&usbotg2 { 162 disable-over-current; 163 dr_mode = "host"; 164 status = "okay"; 165}; 166 167/* SD-Card */ 168&usdhc2 { 169 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 170 pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; 171 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 172 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 173 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 174 vmmc-supply = <®_usdhc2_vmmc>; 175 bus-width = <4>; 176 disable-wp; 177 no-mmc; 178 no-sdio; 179 status = "okay"; 180}; 181 182&iomuxc { 183 pinctrl_eqos: eqosgrp { 184 fsl,pins = < 185 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 186 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 187 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 188 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 189 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 190 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 191 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e 192 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e 193 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x50e 194 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x50e 195 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 196 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e 197 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1002 198 >; 199 }; 200 201 pinctrl_flexcan1: flexcan1grp { 202 fsl,pins = < 203 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 204 MX93_PAD_PDM_CLK__CAN1_TX 0x1382 205 >; 206 }; 207 208 pinctrl_flexcan1_tc: flexcan1tcgrp { 209 fsl,pins = < 210 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e 211 >; 212 }; 213 214 pinctrl_lpi2c2: lpi2c2grp { 215 fsl,pins = < 216 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 217 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 218 >; 219 }; 220 221 pinctrl_lpspi6: lpspi6grp { 222 fsl,pins = < 223 MX93_PAD_GPIO_IO00__GPIO2_IO00 0x386 224 MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe 225 MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x386 226 MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x386 227 >; 228 }; 229 230 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 231 fsl,pins = < 232 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 233 >; 234 }; 235 236 pinctrl_rtc: rtcgrp { 237 fsl,pins = < 238 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e 239 >; 240 }; 241 242 pinctrl_tpm: tpmgrp { 243 fsl,pins = < 244 MX93_PAD_GPIO_IO17__GPIO2_IO17 0x31e 245 >; 246 }; 247 248 pinctrl_uart1: uart1grp { 249 fsl,pins = < 250 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 251 MX93_PAD_UART1_TXD__LPUART1_TX 0x30e 252 >; 253 }; 254 255 pinctrl_uart7: uart7grp { 256 fsl,pins = < 257 MX93_PAD_GPIO_IO08__LPUART7_TX 0x30e 258 MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e 259 MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e 260 MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e 261 >; 262 }; 263 264 pinctrl_usdhc2_cd: usdhc2cdgrp { 265 fsl,pins = < 266 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 267 >; 268 }; 269 270 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 271 pinctrl_usdhc2_default: usdhc2grp { 272 fsl,pins = < 273 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 274 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000178e 275 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001386 276 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001386 277 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001386 278 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 279 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 280 >; 281 }; 282 283 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 284 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 285 fsl,pins = < 286 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 287 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 288 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 289 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 290 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 291 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013be 292 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 293 >; 294 }; 295 296 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 297 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 298 fsl,pins = < 299 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 300 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 301 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 302 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 303 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 304 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 305 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 306 >; 307 }; 308}; 309