1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 * Author: Primoz Fiser <primoz.fiser@norik.com> 5 * 6 * Product homepage: 7 * https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/ 8 */ 9 10/dts-v1/; 11 12#include <dt-bindings/net/ti-dp83867.h> 13#include "imx93-phycore-som.dtsi" 14 15/ { 16 model = "PHYTEC phyBOARD-Nash-i.MX93"; 17 compatible = "phytec,imx93-phyboard-nash", "phytec,imx93-phycore-som", 18 "fsl,imx93"; 19 20 aliases { 21 ethernet1 = &eqos; 22 gpio0 = &gpio1; 23 gpio1 = &gpio2; 24 gpio2 = &gpio3; 25 gpio3 = &gpio4; 26 i2c0 = &lpi2c1; 27 i2c1 = &lpi2c2; 28 mmc0 = &usdhc1; 29 mmc1 = &usdhc2; 30 rtc0 = &i2c_rtc; 31 rtc1 = &bbnsm_rtc; 32 serial0 = &lpuart1; 33 serial1 = &lpuart2; 34 serial2 = &lpuart3; 35 serial3 = &lpuart4; 36 serial4 = &lpuart5; 37 serial5 = &lpuart6; 38 serial6 = &lpuart7; 39 spi0 = &lpspi1; 40 spi1 = &lpspi2; 41 spi2 = &lpspi3; 42 spi3 = &lpspi4; 43 spi4 = &lpspi5; 44 spi5 = &lpspi6; 45 }; 46 47 chosen { 48 stdout-path = &lpuart1; 49 }; 50 51 curr_sens: current-sense { 52 compatible = "current-sense-amplifier"; 53 #io-channel-cells = <0>; 54 io-channels = <&adc1 1>; 55 sense-gain-div = <2>; 56 sense-gain-mult = <50>; 57 sense-resistor-micro-ohms = <35000>; 58 }; 59 60 flexcan1_tc: can-phy0 { 61 compatible = "ti,tcan1042"; 62 #phy-cells = <0>; 63 max-bitrate = <8000000>; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_flexcan1_tc>; 66 standby-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 67 }; 68 69 iio-hwmon { 70 compatible = "iio-hwmon"; 71 io-channels = <&curr_sens 0>; 72 }; 73 74 reg_usdhc2_vmmc: regulator-usdhc2 { 75 compatible = "regulator-fixed"; 76 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 77 enable-active-high; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 80 regulator-name = "VCC_SD"; 81 regulator-max-microvolt = <3300000>; 82 regulator-min-microvolt = <3300000>; 83 }; 84 85 reg_vcc_1v8: regulator-vcc-1v8 { 86 compatible = "regulator-fixed"; 87 regulator-name = "VCC1V8"; 88 regulator-max-microvolt = <1800000>; 89 regulator-min-microvolt = <1800000>; 90 }; 91}; 92 93/* ADC */ 94&adc1 { 95 status = "okay"; 96}; 97 98/* Ethernet */ 99&eqos { 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_eqos>; 102 phy-mode = "rgmii-id"; 103 phy-handle = <ðphy2>; 104 status = "okay"; 105}; 106 107&mdio { 108 ethphy2: ethernet-phy@2 { 109 compatible = "ethernet-phy-ieee802.3-c22"; 110 reg = <2>; 111 interrupt-parent = <&gpio3>; 112 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 113 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 114 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 115 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>; 116 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 117 }; 118}; 119 120/* CAN */ 121&flexcan1 { 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_flexcan1>; 124 phys = <&flexcan1_tc>; 125 status = "okay"; 126}; 127 128/* I2C2 */ 129&lpi2c2 { 130 clock-frequency = <400000>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_lpi2c2>; 133 status = "okay"; 134 135 /* RTC */ 136 i2c_rtc: rtc@52 { 137 compatible = "microcrystal,rv3028"; 138 reg = <0x52>; 139 interrupt-parent = <&gpio4>; 140 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_rtc>; 143 trickle-resistor-ohms = <3000>; 144 wakeup-source; 145 }; 146 147 /* EEPROM */ 148 eeprom@54 { 149 compatible = "atmel,24c32"; 150 reg = <0x54>; 151 pagesize = <32>; 152 vcc-supply = <®_vcc_1v8>; 153 }; 154}; 155 156/* SPI6 */ 157&lpspi6 { 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_lpspi6>; 160 cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 161 status = "okay"; 162 163 /* TPM */ 164 tpm@0 { 165 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 166 reg = <0>; 167 interrupt-parent = <&gpio2>; 168 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_tpm>; 171 spi-max-frequency = <10000000>; 172 }; 173}; 174 175/* Console */ 176&lpuart1 { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_uart1>; 179 status = "okay"; 180}; 181 182/* RS-232/RS-485 */ 183&lpuart7 { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_uart7>; 186 status = "okay"; 187}; 188 189/* USB */ 190&usbotg1 { 191 disable-over-current; 192 dr_mode = "otg"; 193 status = "okay"; 194}; 195 196&usbotg2 { 197 disable-over-current; 198 dr_mode = "host"; 199 status = "okay"; 200}; 201 202/* SD-Card */ 203&usdhc2 { 204 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 205 pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; 206 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 207 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 208 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 209 vmmc-supply = <®_usdhc2_vmmc>; 210 bus-width = <4>; 211 disable-wp; 212 no-mmc; 213 no-sdio; 214 status = "okay"; 215}; 216 217&iomuxc { 218 pinctrl_eqos: eqosgrp { 219 fsl,pins = < 220 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 221 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 222 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 223 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 224 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 225 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 226 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e 227 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e 228 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x50e 229 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x50e 230 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 231 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e 232 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1002 233 >; 234 }; 235 236 pinctrl_flexcan1: flexcan1grp { 237 fsl,pins = < 238 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 239 MX93_PAD_PDM_CLK__CAN1_TX 0x1382 240 >; 241 }; 242 243 pinctrl_flexcan1_tc: flexcan1tcgrp { 244 fsl,pins = < 245 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e 246 >; 247 }; 248 249 pinctrl_lpi2c2: lpi2c2grp { 250 fsl,pins = < 251 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 252 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 253 >; 254 }; 255 256 pinctrl_lpspi6: lpspi6grp { 257 fsl,pins = < 258 MX93_PAD_GPIO_IO00__GPIO2_IO00 0x386 259 MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe 260 MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x386 261 MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x386 262 >; 263 }; 264 265 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 266 fsl,pins = < 267 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 268 >; 269 }; 270 271 pinctrl_rtc: rtcgrp { 272 fsl,pins = < 273 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e 274 >; 275 }; 276 277 pinctrl_tpm: tpmgrp { 278 fsl,pins = < 279 MX93_PAD_GPIO_IO17__GPIO2_IO17 0x31e 280 >; 281 }; 282 283 pinctrl_uart1: uart1grp { 284 fsl,pins = < 285 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 286 MX93_PAD_UART1_TXD__LPUART1_TX 0x30e 287 >; 288 }; 289 290 pinctrl_uart7: uart7grp { 291 fsl,pins = < 292 MX93_PAD_GPIO_IO08__LPUART7_TX 0x30e 293 MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e 294 MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e 295 MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e 296 >; 297 }; 298 299 pinctrl_usdhc2_cd: usdhc2cdgrp { 300 fsl,pins = < 301 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 302 >; 303 }; 304 305 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 306 pinctrl_usdhc2_default: usdhc2grp { 307 fsl,pins = < 308 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 309 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000178e 310 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001386 311 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001386 312 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001386 313 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 314 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 315 >; 316 }; 317 318 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 319 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 320 fsl,pins = < 321 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 322 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 323 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 324 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 325 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 326 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013be 327 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 328 >; 329 }; 330 331 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 332 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 333 fsl,pins = < 334 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 335 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 336 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 337 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 338 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 339 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 340 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 341 >; 342 }; 343}; 344