1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 * Author: Primoz Fiser <primoz.fiser@norik.com> 5 * 6 * Product homepage: 7 * https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/ 8 */ 9 10/dts-v1/; 11 12#include <dt-bindings/net/ti-dp83867.h> 13#include "imx93-phycore-som.dtsi" 14 15/ { 16 model = "PHYTEC phyBOARD-Nash-i.MX93"; 17 compatible = "phytec,imx93-phyboard-nash", "phytec,imx93-phycore-som", 18 "fsl,imx93"; 19 20 aliases { 21 ethernet0 = &fec; 22 ethernet1 = &eqos; 23 rtc0 = &i2c_rtc; 24 rtc1 = &bbnsm_rtc; 25 }; 26 27 chosen { 28 stdout-path = &lpuart1; 29 }; 30 31 flexcan1_tc: can-phy0 { 32 compatible = "ti,tcan1042"; 33 #phy-cells = <0>; 34 max-bitrate = <8000000>; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_flexcan1_tc>; 37 standby-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 38 }; 39 40 reg_usdhc2_vmmc: regulator-usdhc2 { 41 compatible = "regulator-fixed"; 42 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 43 enable-active-high; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 46 regulator-name = "VCC_SD"; 47 regulator-max-microvolt = <3300000>; 48 regulator-min-microvolt = <3300000>; 49 }; 50 51 reg_vcc_1v8: regulator-vcc-1v8 { 52 compatible = "regulator-fixed"; 53 regulator-name = "VCC1V8"; 54 regulator-max-microvolt = <1800000>; 55 regulator-min-microvolt = <1800000>; 56 }; 57 58 reg_vref_1v8: regulator-adc-vref { 59 compatible = "regulator-fixed"; 60 regulator-name = "VREF_1V8"; 61 regulator-min-microvolt = <1800000>; 62 regulator-max-microvolt = <1800000>; 63 }; 64}; 65 66/* ADC */ 67&adc1 { 68 vref-supply = <®_vref_1v8>; 69 status = "okay"; 70}; 71 72/* Ethernet */ 73&eqos { 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_eqos>; 76 phy-mode = "rgmii-id"; 77 phy-handle = <ðphy2>; 78 status = "okay"; 79}; 80 81&mdio { 82 ethphy2: ethernet-phy@2 { 83 compatible = "ethernet-phy-ieee802.3-c22"; 84 reg = <2>; 85 interrupt-parent = <&gpio3>; 86 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 87 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 88 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 89 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>; 90 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 91 }; 92}; 93 94/* CAN */ 95&flexcan1 { 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_flexcan1>; 98 phys = <&flexcan1_tc>; 99 status = "okay"; 100}; 101 102/* I2C2 */ 103&lpi2c2 { 104 clock-frequency = <400000>; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_lpi2c2>; 107 status = "okay"; 108 109 /* RTC */ 110 i2c_rtc: rtc@52 { 111 compatible = "microcrystal,rv3028"; 112 reg = <0x52>; 113 interrupt-parent = <&gpio4>; 114 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_rtc>; 117 trickle-resistor-ohms = <3000>; 118 wakeup-source; 119 }; 120 121 /* EEPROM */ 122 eeprom@54 { 123 compatible = "atmel,24c32"; 124 reg = <0x54>; 125 pagesize = <32>; 126 vcc-supply = <®_vcc_1v8>; 127 }; 128}; 129 130/* SPI6 */ 131&lpspi6 { 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_lpspi6>; 134 cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 135 status = "okay"; 136 137 /* TPM */ 138 tpm@0 { 139 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 140 reg = <0>; 141 interrupt-parent = <&gpio2>; 142 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_tpm>; 145 spi-max-frequency = <10000000>; 146 }; 147}; 148 149/* Console */ 150&lpuart1 { 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_uart1>; 153 status = "okay"; 154}; 155 156/* RS-232/RS-485 */ 157&lpuart7 { 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_uart7>; 160 status = "okay"; 161}; 162 163/* USB */ 164&usbotg1 { 165 disable-over-current; 166 dr_mode = "otg"; 167 status = "okay"; 168}; 169 170&usbotg2 { 171 disable-over-current; 172 dr_mode = "host"; 173 status = "okay"; 174}; 175 176/* SD-Card */ 177&usdhc2 { 178 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 179 pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; 180 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 181 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 182 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 183 vmmc-supply = <®_usdhc2_vmmc>; 184 bus-width = <4>; 185 disable-wp; 186 no-mmc; 187 no-sdio; 188 status = "okay"; 189}; 190 191&iomuxc { 192 pinctrl_eqos: eqosgrp { 193 fsl,pins = < 194 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 195 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 196 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 197 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 198 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 199 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 200 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e 201 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e 202 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x50e 203 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x50e 204 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 205 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e 206 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1002 207 >; 208 }; 209 210 pinctrl_flexcan1: flexcan1grp { 211 fsl,pins = < 212 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 213 MX93_PAD_PDM_CLK__CAN1_TX 0x1382 214 >; 215 }; 216 217 pinctrl_flexcan1_tc: flexcan1tcgrp { 218 fsl,pins = < 219 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e 220 >; 221 }; 222 223 pinctrl_lpi2c2: lpi2c2grp { 224 fsl,pins = < 225 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 226 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 227 >; 228 }; 229 230 pinctrl_lpspi6: lpspi6grp { 231 fsl,pins = < 232 MX93_PAD_GPIO_IO00__GPIO2_IO00 0x386 233 MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe 234 MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x386 235 MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x386 236 >; 237 }; 238 239 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 240 fsl,pins = < 241 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 242 >; 243 }; 244 245 pinctrl_rtc: rtcgrp { 246 fsl,pins = < 247 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e 248 >; 249 }; 250 251 pinctrl_tpm: tpmgrp { 252 fsl,pins = < 253 MX93_PAD_GPIO_IO17__GPIO2_IO17 0x31e 254 >; 255 }; 256 257 pinctrl_uart1: uart1grp { 258 fsl,pins = < 259 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 260 MX93_PAD_UART1_TXD__LPUART1_TX 0x30e 261 >; 262 }; 263 264 pinctrl_uart7: uart7grp { 265 fsl,pins = < 266 MX93_PAD_GPIO_IO08__LPUART7_TX 0x30e 267 MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e 268 MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e 269 MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e 270 >; 271 }; 272 273 pinctrl_usdhc2_cd: usdhc2cdgrp { 274 fsl,pins = < 275 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 276 >; 277 }; 278 279 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 280 pinctrl_usdhc2_default: usdhc2grp { 281 fsl,pins = < 282 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 283 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000178e 284 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001386 285 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001386 286 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001386 287 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 288 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 289 >; 290 }; 291 292 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 293 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 294 fsl,pins = < 295 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 296 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 297 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 298 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 299 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 300 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013be 301 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 302 >; 303 }; 304 305 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 306 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 307 fsl,pins = < 308 MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e 309 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 310 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 311 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 312 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 313 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 314 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 315 >; 316 }; 317}; 318