1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright (C) 2024 Kontron Electronics GmbH 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include "imx93.dtsi" 8 9/ { 10 model = "Kontron OSM-S i.MX93"; 11 compatible = "kontron,imx93-osm-s", "fsl,imx93"; 12 13 aliases { 14 rtc0 = &rv3028; 15 rtc1 = &bbnsm_rtc; 16 }; 17 18 memory@40000000 { 19 device_type = "memory"; 20 reg = <0x0 0x40000000 0 0x80000000>; 21 }; 22 23 chosen { 24 stdout-path = &lpuart1; 25 }; 26 27 reg_usdhc2_vcc: regulator-usdhc2-vcc { 28 compatible = "regulator-fixed"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>; 31 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 32 enable-active-high; 33 regulator-min-microvolt = <3300000>; 34 regulator-max-microvolt = <3300000>; 35 regulator-name = "VCC_SDIO_A"; 36 }; 37 38 reg_vdd_carrier: regulator-vdd-carrier { 39 compatible = "regulator-fixed"; 40 pinctrl-names = "default"; 41 pinctrl-0 = <&pinctrl_reg_vdd_carrier>; 42 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 43 enable-active-high; 44 regulator-always-on; 45 regulator-boot-on; 46 regulator-name = "VDD_CARRIER"; 47 48 regulator-state-standby { 49 regulator-on-in-suspend; 50 }; 51 52 regulator-state-mem { 53 regulator-off-in-suspend; 54 }; 55 56 regulator-state-disk { 57 regulator-off-in-suspend; 58 }; 59 }; 60}; 61 62&flexcan1 { /* OSM-S CAN_A */ 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_flexcan1>; 65}; 66 67&flexcan2 { /* OSM-S CAN_B */ 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_flexcan2>; 70}; 71 72&gpio1 { 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_gpio1>; 75 gpio-line-names = "", "", "I2C_A_SCL", "I2C_A_SDA", 76 "UART_CON_RX", "UART_CON_TX", "UART_C_RX", "UART_C_TX", 77 "CAN_A_TX", "CAN_A_RX", "GPIO_A_0", "SPI_A_CS0", 78 "SPI_A_SDI", "SPI_A_SCK","SPI_A_SDO"; 79}; 80 81&gpio2 { 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_gpio2>; 84 gpio-line-names = "I2C_B_SDA", "I2C_B_SCL", "GPIO_B_1", "GPIO_A_2", 85 "UART_B_TX", "UART_B_RX", "UART_B_RTS", "UART_B_CTS", 86 "UART_A_TX", "UART_A_RX", "UART_A_RTS", "UART_A_CTS", 87 "SPI_B_CS0", "SPI_B_SDI", "SPI_B_SDO", "SPI_B_SCK", 88 "I2S_BITCLK", "I2S_MCLK", "GPIO_A_1", "I2S_A_DATA_OUT", 89 "I2S_A_DATA_IN", "PWM_2", "GPIO_A_3", "PWM_1", 90 "PWM_0", "CAN_B_TX", "I2S_LRCLK", "CAN_B_RX", "GPIO_A_4", 91 "GPIO_A_5"; 92}; 93 94&gpio3 { 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_gpio3>; 97 gpio-line-names = "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", 98 "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", 99 "", "", "", "", 100 "", "", "", "", 101 "", "", "", "", 102 "SDIO_B_CLK", "SDIO_B_CMD", "SDIO_B_D0", "SDIO_B_D1", 103 "SDIO_B_D2", "SDIO_B_D3", "GPIO_A_6", "GPIO_A_7"; 104}; 105 106&gpio4 { 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_gpio4>; 109 gpio-line-names = "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD4", "ETH_B_TXD3", 110 "ETH_B_TXD2", "ETH_B_TXD1", "ETH_B_TX_EN", "ETH_B_TX_CLK", 111 "ETH_B_RX_CTL", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1", 112 "ETH_B_RXD2", "ETH_B_RXD3", "ETH_MDC", "ETH_MDIO", 113 "ETH_A_TXD3", "ETH_A_TXD2", "ETH_A_TXD1", "ETH_A_TXD0", 114 "ETH_A_TX_EN", "ETH_A_TX_CLK", "ETH_A_RX_CTL", "ETH_A_RX_CLK", 115 "ETH_A_RXD0", "ETH_A_RXD1", "ETH_A_RXD2", "ETH_A_RXD3", 116 "GPIO_B_0", "CARRIER_PWR_EN"; 117}; 118 119&lpi2c1 { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_lpi2c1>; 122 status = "okay"; 123 124 pca9451: pmic@25 { 125 compatible = "nxp,pca9451a"; 126 reg = <0x25>; 127 nxp,i2c-lt-enable; 128 129 regulators { 130 reg_vdd_soc: BUCK1 { /* dual phase with BUCK3 */ 131 regulator-name = "+0V8_VDD_SOC (BUCK1)"; 132 regulator-min-microvolt = <650000>; 133 regulator-max-microvolt = <950000>; 134 regulator-boot-on; 135 regulator-always-on; 136 regulator-ramp-delay = <3125>; 137 }; 138 139 reg_vddq_ddr: BUCK2 { 140 regulator-name = "+0V6_VDDQ_DDR (BUCK2)"; 141 regulator-min-microvolt = <600000>; 142 regulator-max-microvolt = <600000>; 143 regulator-boot-on; 144 regulator-always-on; 145 regulator-ramp-delay = <3125>; 146 }; 147 148 reg_vdd_3v3: BUCK4 { 149 regulator-name = "+3V3 (BUCK4)"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 regulator-boot-on; 153 regulator-always-on; 154 }; 155 156 reg_vdd_1v8: BUCK5 { 157 regulator-name = "+1V8 (BUCK5)"; 158 regulator-min-microvolt = <1800000>; 159 regulator-max-microvolt = <1800000>; 160 regulator-boot-on; 161 regulator-always-on; 162 }; 163 164 reg_nvcc_dram: BUCK6 { 165 regulator-name = "+1V1_NVCC_DRAM (BUCK6)"; 166 regulator-min-microvolt = <1100000>; 167 regulator-max-microvolt = <1100000>; 168 regulator-boot-on; 169 regulator-always-on; 170 }; 171 172 reg_nvcc_snvs: LDO1 { 173 regulator-name = "+1V8_NVCC_SNVS (LDO1)"; 174 regulator-min-microvolt = <1800000>; 175 regulator-max-microvolt = <1800000>; 176 regulator-boot-on; 177 regulator-always-on; 178 }; 179 180 reg_vdd_ana: LDO4 { 181 regulator-name = "+0V8_VDD_ANA (LDO4)"; 182 regulator-min-microvolt = <800000>; 183 regulator-max-microvolt = <800000>; 184 regulator-boot-on; 185 regulator-always-on; 186 }; 187 188 reg_nvcc_sd: LDO5 { 189 regulator-name = "NVCC_SD (LDO5)"; 190 regulator-min-microvolt = <1800000>; 191 regulator-max-microvolt = <3300000>; 192 nxp,sd-vsel-fixed-low; 193 }; 194 }; 195 }; 196 197 eeprom@50 { 198 compatible = "onnn,n24s64b", "atmel,24c64"; 199 reg = <0x50>; 200 pagesize = <32>; 201 size = <8192>; 202 num-addresses = <1>; 203 }; 204 205 rv3028: rtc@52 { 206 compatible = "microcrystal,rv3028"; 207 reg = <0x52>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_rtc>; 210 interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>; 211 }; 212}; 213 214&lpi2c2 { /* OSM-S I2C_A */ 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_lpi2c2>; 217}; 218 219&lpi2c3 { /* OSM-S I2C_B */ 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_lpi2c3>; 222}; 223 224&lpspi1 { /* OSM-S SPI_A */ 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_lpspi1>; 227 cs-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 228}; 229 230&lpspi8 { /* OSM-S SPI_B */ 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_lpspi8>; 233 cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 234}; 235 236&lpuart1 { /* OSM-S UART_CON */ 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_lpuart1>; 239}; 240 241&lpuart2 { /* OSM-S UART_C */ 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_lpuart2>; 244}; 245 246&lpuart6 { /* OSM-S UART_B */ 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_lpuart6>; 249}; 250 251&lpuart7 { /* OSM-S UART_A */ 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_lpuart7>; 254}; 255 256&tpm3 { /* OSM-S PWM_0 */ 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_tpm3>; 259}; 260 261&tpm4 { /* OSM-S PWM_2 */ 262 pinctrl-names = "default"; 263 pinctrl-0 = <&pinctrl_tpm4>; 264}; 265 266&tpm6 { /* OSM-S PWM_1 */ 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_tpm6>; 269}; 270 271&usdhc1 { /* eMMC */ 272 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 273 pinctrl-0 = <&pinctrl_usdhc1>; 274 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 275 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 276 vmmc-supply = <®_vdd_3v3>; 277 vqmmc-supply = <®_vdd_1v8>; 278 bus-width = <8>; 279 non-removable; 280 status = "okay"; 281}; 282 283&usdhc2 { /* OSM-S SDIO_A */ 284 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 285 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 286 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 287 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 288 vmmc-supply = <®_usdhc2_vcc>; 289 vqmmc-supply = <®_nvcc_sd>; 290 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 291}; 292 293&usdhc3 { /* OSM-S SDIO_B */ 294 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 295 pinctrl-0 = <&pinctrl_usdhc3>; 296 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 297 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 298 vqmmc-supply = <®_vdd_1v8>; 299}; 300 301&wdog3 { 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_wdog>; 304 fsl,ext-reset-output; 305 status = "okay"; 306}; 307 308&iomuxc { 309 pinctrl_enet_rgmii: enetrgmiigrp { 310 fsl,pins = < 311 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e /* ETH_MDC */ 312 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e /* ETH_MDIO */ 313 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e /* ETH_A_(S)(R)(G)MII_RXD0 */ 314 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e /* ETH_A_(S)(R)(G)MII_RXD1 */ 315 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e /* ETH_A_(R)(G)MII_RXD2 */ 316 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e /* ETH_A_(R)(G)MII_RXD3 */ 317 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe /* ETH_A_(R)(G)MII_RX_CLK */ 318 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e /* ETH_A_(R)(G)MII_RX_DV(_ER) */ 319 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e /* ETH_A_(S)(R)(G)MII_TXD0 */ 320 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e /* ETH_A_(S)(R)(G)MII_TXD1 */ 321 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e /* ETH_A_(S)(R)(G)MII_TXD2 */ 322 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e /* ETH_A_(S)(R)(G)MII_TXD3 */ 323 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe /* ETH_A_(R)(G)MII_TX_CLK */ 324 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e /* ETH_A_(R)(G)MII_TX_EN(_ER) */ 325 >; 326 }; 327 328 pinctrl_eqos_rgmii: eqosrgmiigrp { 329 fsl,pins = < 330 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e /* ETH_B_MDC */ 331 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e /* ETH_B_MDIO */ 332 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e /* ETH_B_(S)(R)(G)MII_RXD0 */ 333 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e /* ETH_B_(S)(R)(G)MII_RXD1 */ 334 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e /* ETH_B_(R)(G)MII_RXD2 */ 335 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e /* ETH_B_(R)(G)MII_RXD3 */ 336 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x57e /* ETH_B_(R)(G)MII_RX_CLK */ 337 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e /* ETH_B_(R)(G)MII_RX_DV(_ER) */ 338 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e /* ETH_B_(S)(R)(G)MII_TXD0 */ 339 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e /* ETH_B_(S)(R)(G)MII_TXD1 */ 340 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e /* ETH_B_(S)(R)(G)MII_TXD2 */ 341 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e /* ETH_B_(S)(R)(G)MII_TXD3 */ 342 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x57e /* ETH_B_(R)(G)MII_TX_CLK */ 343 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e /* ETH_B_(R)(G)MII_TX_EN(_ER) */ 344 >; 345 }; 346 347 pinctrl_flexcan1: flexcan1grp { 348 fsl,pins = < 349 MX93_PAD_PDM_CLK__CAN1_TX 0x139e /* CAN_A_TX */ 350 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e /* CAN_A_RX */ 351 >; 352 }; 353 354 pinctrl_flexcan2: flexcan2grp { 355 fsl,pins = < 356 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e /* CAN_B_TX */ 357 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e /* CAN_B_RX */ 358 >; 359 }; 360 361 pinctrl_gpio1: gpio1grp { 362 fsl,pins = < 363 MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e /* GPIO_A_0 */ 364 >; 365 }; 366 367 pinctrl_gpio2: gpio2grp { 368 fsl,pins = < 369 MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e /* GPIO_A_1 */ 370 MX93_PAD_GPIO_IO03__GPIO2_IO03 0x31e /* GPIO_A_2 */ 371 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e /* GPIO_A_3 */ 372 MX93_PAD_GPIO_IO28__GPIO2_IO28 0x31e /* GPIO_A_4 */ 373 MX93_PAD_GPIO_IO29__GPIO2_IO29 0x31e /* GPIO_A_5 */ 374 MX93_PAD_GPIO_IO02__GPIO2_IO02 0x31e /* GPIO_B_1 */ 375 >; 376 }; 377 378 pinctrl_gpio3: gpio3grp { 379 fsl,pins = < 380 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e /* GPIO_A_6 */ 381 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e /* GPIO_A_7 */ 382 >; 383 }; 384 385 pinctrl_gpio4: gpio4grp { 386 fsl,pins = < 387 MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e /* GPIO_B_0 */ 388 >; 389 }; 390 391 pinctrl_lpi2c1: lpi2c1grp { 392 fsl,pins = < 393 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 394 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 395 >; 396 }; 397 398 pinctrl_lpi2c2: lpi2c2grp { 399 fsl,pins = < 400 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e /* I2C_A_SCL */ 401 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e /* I2C_A_SDA */ 402 >; 403 }; 404 405 pinctrl_lpi2c3: lpi2c3grp { 406 fsl,pins = < 407 MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x40000b9e /* I2C_B_SCL */ 408 MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x40000b9e /* I2C_B_SDA */ 409 >; 410 }; 411 412 pinctrl_lpspi1: lpspi1grp { 413 fsl,pins = < 414 MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x3fe /* SPI_A_SDI_(IO0) */ 415 MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x3fe /* SPI_A_SDO_(IO1) */ 416 MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x3fe /* SPI_A_SCK */ 417 MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x3fe /* SPI_A_CS0# */ 418 >; 419 }; 420 421 pinctrl_lpspi8: lpspi8grp { 422 fsl,pins = < 423 MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x3fe /* SPI_B_SDI */ 424 MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x3fe /* SPI_B_SDO */ 425 MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x3fe /* SPI_B_SCK */ 426 MX93_PAD_GPIO_IO12__GPIO2_IO12 0x3fe /* SPI_B_CS0# */ 427 >; 428 }; 429 430 pinctrl_lpuart1: lpuart1grp { 431 fsl,pins = < 432 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e /* UART_CON_RX */ 433 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e /* UART_CON_TX */ 434 >; 435 }; 436 437 pinctrl_lpuart2: lpuart2grp { 438 fsl,pins = < 439 MX93_PAD_UART2_RXD__LPUART2_RX 0x31e /* UART_C_RX */ 440 MX93_PAD_UART2_TXD__LPUART2_TX 0x31e /* UART_C_TX */ 441 >; 442 }; 443 444 pinctrl_lpuart6: lpuart6grp { 445 fsl,pins = < 446 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e /* UART_B_RX */ 447 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e /* UART_B_TX */ 448 MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e /* UART_B_CTS */ 449 MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x31e /* UART_B_RTS */ 450 >; 451 }; 452 453 pinctrl_lpuart7: lpuart7grp { 454 fsl,pins = < 455 MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e /* UART_A_RX */ 456 MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e /* UART_A_TX */ 457 MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e /* UART_A_CTS */ 458 MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e /* UART_A_RTS */ 459 >; 460 }; 461 462 pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { 463 fsl,pins = < 464 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e /* SDIO_A_PWR_EN */ 465 >; 466 }; 467 468 pinctrl_reg_vdd_carrier: regvddcarriergrp { 469 fsl,pins = < 470 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e /* CARRIER_PWR_EN */ 471 >; 472 }; 473 474 pinctrl_rtc: rtcgrp { 475 fsl,pins = < 476 MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x31e 477 >; 478 }; 479 480 pinctrl_sai3: sai3grp { 481 fsl,pins = < 482 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e /* I2S_A_DATA_IN */ 483 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e /* I2S_A_DATA_OUT */ 484 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e /* I2S_MCLK */ 485 MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e /* I2S_LRCLK */ 486 MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e /* I2S_BITCLK */ 487 >; 488 }; 489 490 pinctrl_tpm3: tpm3grp { 491 fsl,pins = < 492 MX93_PAD_GPIO_IO24__TPM3_CH3 0x57e /* PWM_0 */ 493 >; 494 }; 495 496 pinctrl_tpm4: tpm4grp { 497 fsl,pins = < 498 MX93_PAD_GPIO_IO21__TPM4_CH1 0x57e /* PWM_2 */ 499 >; 500 }; 501 502 pinctrl_tpm6: tpm6grp { 503 fsl,pins = < 504 MX93_PAD_GPIO_IO23__TPM6_CH1 0x57e /* PWM_1 */ 505 >; 506 }; 507 508 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 509 pinctrl_usdhc1: usdhc1grp { 510 fsl,pins = < 511 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 512 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 513 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 514 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 515 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 516 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 517 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 518 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 519 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 520 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 521 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 522 >; 523 }; 524 525 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 526 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 527 fsl,pins = < 528 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 529 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 530 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 531 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 532 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 533 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 534 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 535 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 536 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 537 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 538 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 539 >; 540 }; 541 542 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 543 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 544 fsl,pins = < 545 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 546 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 547 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 548 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 549 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 550 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 551 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 552 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 553 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 554 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 555 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 556 >; 557 }; 558 559 pinctrl_usdhc2: usdhc2grp { 560 fsl,pins = < 561 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 /* SDIO_A_CLK */ 562 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 /* SDIO_A_CMD */ 563 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 /* SDIO_A_D0 */ 564 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 /* SDIO_A_D1 */ 565 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 /* SDIO_A_D2 */ 566 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 /* SDIO_A_D3 */ 567 >; 568 }; 569 570 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 571 fsl,pins = < 572 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e /* SDIO_A_CLK */ 573 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e /* SDIO_A_CMD */ 574 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e /* SDIO_A_D0 */ 575 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e /* SDIO_A_D1 */ 576 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e /* SDIO_A_D2 */ 577 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e /* SDIO_A_D3 */ 578 >; 579 }; 580 581 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 582 fsl,pins = < 583 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe /* SDIO_A_CLK */ 584 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe /* SDIO_A_CMD */ 585 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe /* SDIO_A_D0 */ 586 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe /* SDIO_A_D1 */ 587 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe /* SDIO_A_D2 */ 588 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe /* SDIO_A_D3 */ 589 >; 590 }; 591 592 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 593 fsl,pins = < 594 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e /* SDIO_A_CD# */ 595 >; 596 }; 597 598 pinctrl_usdhc3: usdhc3grp { 599 fsl,pins = < 600 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 /* SDIO_B_CLK */ 601 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 /* SDIO_B_CMD */ 602 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 /* SDIO_B_D0 */ 603 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 /* SDIO_B_D1 */ 604 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 /* SDIO_B_D2 */ 605 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 /* SDIO_B_D3 */ 606 >; 607 }; 608 609 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 610 fsl,pins = < 611 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e /* SDIO_B_CLK */ 612 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e /* SDIO_B_CMD */ 613 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e /* SDIO_B_D0 */ 614 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e /* SDIO_B_D1 */ 615 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e /* SDIO_B_D2 */ 616 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e /* SDIO_B_D3 */ 617 >; 618 }; 619 620 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 621 fsl,pins = < 622 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe /* SDIO_B_CLK */ 623 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe /* SDIO_B_CMD */ 624 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe /* SDIO_B_D0 */ 625 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe /* SDIO_B_D1 */ 626 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe /* SDIO_B_D2 */ 627 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe /* SDIO_B_D3 */ 628 >; 629 }; 630 631 pinctrl_wdog: wdoggrp { 632 fsl,pins = < 633 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0xc6 634 >; 635 }; 636}; 637