1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 9x9 Quick Start Board"; 13 compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; 14 15 chosen { 16 stdout-path = &lpuart1; 17 }; 18 19 reserved-memory { 20 #address-cells = <2>; 21 #size-cells = <2>; 22 ranges; 23 24 linux,cma { 25 compatible = "shared-dma-pool"; 26 reusable; 27 size = <0 0x10000000>; 28 linux,cma-default; 29 }; 30 31 vdev0vring0: vdev0vring0@a4000000 { 32 reg = <0 0xa4000000 0 0x8000>; 33 no-map; 34 }; 35 36 vdev0vring1: vdev0vring1@a4008000 { 37 reg = <0 0xa4008000 0 0x8000>; 38 no-map; 39 }; 40 41 vdev1vring0: vdev1vring0@a4010000 { 42 reg = <0 0xa4010000 0 0x8000>; 43 no-map; 44 }; 45 46 vdev1vring1: vdev1vring1@a4018000 { 47 reg = <0 0xa4018000 0 0x8000>; 48 no-map; 49 }; 50 51 rsc_table: rsc-table@2021e000 { 52 reg = <0 0x2021e000 0 0x1000>; 53 no-map; 54 }; 55 56 vdevbuffer: vdevbuffer@a4020000 { 57 compatible = "shared-dma-pool"; 58 reg = <0 0xa4020000 0 0x100000>; 59 no-map; 60 }; 61 62 }; 63 64 reg_vref_1v8: regulator-adc-vref { 65 compatible = "regulator-fixed"; 66 regulator-name = "VREF_1V8"; 67 regulator-min-microvolt = <1800000>; 68 regulator-max-microvolt = <1800000>; 69 }; 70 71 reg_rpi_3v3: regulator-rpi { 72 compatible = "regulator-fixed"; 73 regulator-name = "VDD_RPI_3V3"; 74 regulator-min-microvolt = <3300000>; 75 regulator-max-microvolt = <3300000>; 76 gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>; 77 enable-active-high; 78 }; 79 80 reg_usdhc2_vmmc: regulator-usdhc2 { 81 compatible = "regulator-fixed"; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 84 regulator-name = "VSD_3V3"; 85 regulator-min-microvolt = <3300000>; 86 regulator-max-microvolt = <3300000>; 87 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 88 enable-active-high; 89 off-on-delay-us = <12000>; 90 }; 91}; 92 93&adc1 { 94 vref-supply = <®_vref_1v8>; 95 status = "okay"; 96}; 97 98&cm33 { 99 mbox-names = "tx", "rx", "rxdb"; 100 mboxes = <&mu1 0 1>, 101 <&mu1 1 1>, 102 <&mu1 3 1>; 103 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 104 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 105 status = "okay"; 106}; 107 108&eqos { 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_eqos>; 111 phy-mode = "rgmii-id"; 112 phy-handle = <ðphy1>; 113 status = "okay"; 114 115 mdio { 116 compatible = "snps,dwmac-mdio"; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 clock-frequency = <5000000>; 120 121 ethphy1: ethernet-phy@1 { 122 compatible = "ethernet-phy-ieee802.3-c22"; 123 reg = <1>; 124 eee-broken-1000t; 125 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 126 reset-assert-us = <10000>; 127 reset-deassert-us = <80000>; 128 realtek,clkout-disable; 129 }; 130 }; 131}; 132 133&lpi2c1 { 134 clock-frequency = <400000>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_lpi2c1>; 137 status = "okay"; 138 139 ptn5110: tcpc@50 { 140 compatible = "nxp,ptn5110", "tcpci"; 141 reg = <0x50>; 142 interrupt-parent = <&gpio3>; 143 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 144 145 typec1_con: connector { 146 compatible = "usb-c-connector"; 147 label = "USB-C"; 148 power-role = "dual"; 149 data-role = "dual"; 150 try-power-role = "sink"; 151 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 152 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 153 PDO_VAR(5000, 20000, 3000)>; 154 op-sink-microwatt = <15000000>; 155 self-powered; 156 157 ports { 158 #address-cells = <1>; 159 #size-cells = <0>; 160 161 port@0 { 162 reg = <0>; 163 164 typec1_dr_sw: endpoint { 165 remote-endpoint = <&usb1_drd_sw>; 166 }; 167 }; 168 }; 169 }; 170 }; 171 172 rtc@53 { 173 compatible = "nxp,pcf2131"; 174 reg = <0x53>; 175 interrupt-parent = <&pcal6524>; 176 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 177 }; 178}; 179 180&lpi2c2 { 181 clock-frequency = <400000>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_lpi2c2>; 184 status = "okay"; 185 186 pcal6524: gpio@22 { 187 compatible = "nxp,pcal6524"; 188 reg = <0x22>; 189 gpio-controller; 190 #gpio-cells = <2>; 191 interrupt-controller; 192 #interrupt-cells = <2>; 193 interrupt-parent = <&gpio3>; 194 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_pcal6524>; 197 }; 198 199 pmic@25 { 200 compatible = "nxp,pca9451a"; 201 reg = <0x25>; 202 interrupt-parent = <&pcal6524>; 203 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 204 205 regulators { 206 buck1: BUCK1 { 207 regulator-name = "BUCK1"; 208 regulator-min-microvolt = <650000>; 209 regulator-max-microvolt = <2237500>; 210 regulator-boot-on; 211 regulator-always-on; 212 regulator-ramp-delay = <3125>; 213 }; 214 215 buck2: BUCK2 { 216 regulator-name = "BUCK2"; 217 regulator-min-microvolt = <600000>; 218 regulator-max-microvolt = <2187500>; 219 regulator-boot-on; 220 regulator-always-on; 221 regulator-ramp-delay = <3125>; 222 }; 223 224 buck4: BUCK4{ 225 regulator-name = "BUCK4"; 226 regulator-min-microvolt = <600000>; 227 regulator-max-microvolt = <3400000>; 228 regulator-boot-on; 229 regulator-always-on; 230 }; 231 232 buck5: BUCK5{ 233 regulator-name = "BUCK5"; 234 regulator-min-microvolt = <600000>; 235 regulator-max-microvolt = <3400000>; 236 regulator-boot-on; 237 regulator-always-on; 238 }; 239 240 buck6: BUCK6 { 241 regulator-name = "BUCK6"; 242 regulator-min-microvolt = <600000>; 243 regulator-max-microvolt = <3400000>; 244 regulator-boot-on; 245 regulator-always-on; 246 }; 247 248 ldo1: LDO1 { 249 regulator-name = "LDO1"; 250 regulator-min-microvolt = <1600000>; 251 regulator-max-microvolt = <3300000>; 252 regulator-boot-on; 253 regulator-always-on; 254 }; 255 256 ldo4: LDO4 { 257 regulator-name = "LDO4"; 258 regulator-min-microvolt = <800000>; 259 regulator-max-microvolt = <3300000>; 260 regulator-boot-on; 261 regulator-always-on; 262 }; 263 264 ldo5: LDO5 { 265 regulator-name = "LDO5"; 266 regulator-min-microvolt = <1800000>; 267 regulator-max-microvolt = <3300000>; 268 regulator-boot-on; 269 regulator-always-on; 270 }; 271 }; 272 }; 273}; 274 275&lpuart1 { /* console */ 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_uart1>; 278 status = "okay"; 279}; 280 281&mu1 { 282 status = "okay"; 283}; 284 285&mu2 { 286 status = "okay"; 287}; 288 289&usbotg1 { 290 dr_mode = "otg"; 291 hnp-disable; 292 srp-disable; 293 adp-disable; 294 usb-role-switch; 295 disable-over-current; 296 samsung,picophy-pre-emp-curr-control = <3>; 297 samsung,picophy-dc-vol-level-adjust = <7>; 298 status = "okay"; 299 300 port { 301 usb1_drd_sw: endpoint { 302 remote-endpoint = <&typec1_dr_sw>; 303 }; 304 }; 305}; 306 307&usdhc1 { 308 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 309 pinctrl-0 = <&pinctrl_usdhc1>; 310 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 311 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 312 bus-width = <8>; 313 non-removable; 314 status = "okay"; 315}; 316 317&usdhc2 { 318 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 319 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 320 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 321 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 322 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 323 vmmc-supply = <®_usdhc2_vmmc>; 324 bus-width = <4>; 325 no-mmc; 326 status = "okay"; 327}; 328 329&wdog3 { 330 status = "okay"; 331}; 332 333&iomuxc { 334 pinctrl_eqos: eqosgrp { 335 fsl,pins = < 336 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 337 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 338 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 339 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 340 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 341 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 342 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 343 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 344 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 345 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 346 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 347 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 348 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 349 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 350 >; 351 }; 352 353 pinctrl_lpi2c1: lpi2c1grp { 354 fsl,pins = < 355 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 356 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 357 >; 358 }; 359 360 pinctrl_lpi2c2: lpi2c2grp { 361 fsl,pins = < 362 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 363 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 364 >; 365 }; 366 367 pinctrl_pcal6524: pcal6524grp { 368 fsl,pins = < 369 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 370 >; 371 }; 372 373 pinctrl_uart1: uart1grp { 374 fsl,pins = < 375 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 376 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 377 >; 378 }; 379 380 pinctrl_uart5: uart5grp { 381 fsl,pins = < 382 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 383 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 384 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 385 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 386 >; 387 }; 388 389 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 390 pinctrl_usdhc1: usdhc1grp { 391 fsl,pins = < 392 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 393 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 394 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 395 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 396 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 397 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 398 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 399 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 400 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 401 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 402 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 403 >; 404 }; 405 406 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 407 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 408 fsl,pins = < 409 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 410 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 411 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 412 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 413 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 414 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 415 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 416 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 417 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 418 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 419 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 420 >; 421 }; 422 423 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 424 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 425 fsl,pins = < 426 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 427 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 428 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 429 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 430 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 431 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 432 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 433 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 434 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 435 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 436 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 437 >; 438 }; 439 440 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 441 fsl,pins = < 442 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 443 >; 444 }; 445 446 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 447 fsl,pins = < 448 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 449 >; 450 }; 451 452 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 453 pinctrl_usdhc2: usdhc2grp { 454 fsl,pins = < 455 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 456 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 457 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 458 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 459 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 460 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 461 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 462 >; 463 }; 464 465 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 466 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 467 fsl,pins = < 468 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 469 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 470 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 471 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 472 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 473 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 474 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 475 >; 476 }; 477 478 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 479 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 480 fsl,pins = < 481 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 482 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 483 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 484 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 485 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 486 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 487 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 488 >; 489 }; 490}; 491