1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 14X14 EVK board"; 13 compatible = "fsl,imx93-14x14-evk", "fsl,imx93"; 14 15 aliases { 16 ethernet0 = &fec; 17 ethernet1 = &eqos; 18 gpio0 = &gpio1; 19 gpio1 = &gpio2; 20 gpio2 = &gpio3; 21 i2c0 = &lpi2c1; 22 i2c1 = &lpi2c2; 23 i2c2 = &lpi2c3; 24 mmc0 = &usdhc1; 25 mmc1 = &usdhc2; 26 rtc0 = &bbnsm_rtc; 27 serial0 = &lpuart1; 28 }; 29 30 chosen { 31 stdout-path = &lpuart1; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 linux,cma { 40 compatible = "shared-dma-pool"; 41 reusable; 42 alloc-ranges = <0 0x80000000 0 0x40000000>; 43 size = <0 0x10000000>; 44 linux,cma-default; 45 }; 46 47 vdev0vring0: vdev0vring0@a4000000 { 48 reg = <0 0xa4000000 0 0x8000>; 49 no-map; 50 }; 51 52 vdev0vring1: vdev0vring1@a4008000 { 53 reg = <0 0xa4008000 0 0x8000>; 54 no-map; 55 }; 56 57 vdev1vring0: vdev1vring0@a4010000 { 58 reg = <0 0xa4010000 0 0x8000>; 59 no-map; 60 }; 61 62 vdev1vring1: vdev1vring1@a4018000 { 63 reg = <0 0xa4018000 0 0x8000>; 64 no-map; 65 }; 66 67 rsc_table: rsc-table@2021e000 { 68 reg = <0 0x2021e000 0 0x1000>; 69 no-map; 70 }; 71 72 vdevbuffer: vdevbuffer@a4020000 { 73 compatible = "shared-dma-pool"; 74 reg = <0 0xa4020000 0 0x100000>; 75 no-map; 76 }; 77 }; 78 79 reg_can1_stby: regulator-can1-stby { 80 compatible = "regulator-fixed"; 81 regulator-name = "can1-stby"; 82 regulator-min-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>; 84 gpio = <&pcal6524_2 10 GPIO_ACTIVE_HIGH>; 85 enable-active-high; 86 vin-supply = <®_can1_en>; 87 }; 88 89 reg_can1_en: regulator-can1-en { 90 compatible = "regulator-fixed"; 91 regulator-name = "can1-en"; 92 regulator-min-microvolt = <3300000>; 93 regulator-max-microvolt = <3300000>; 94 gpio = <&pcal6524_2 12 GPIO_ACTIVE_HIGH>; 95 enable-active-high; 96 }; 97 98 reg_can2_stby: regulator-can2-stby { 99 compatible = "regulator-fixed"; 100 regulator-name = "can2-stby"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 gpio = <&pcal6524_2 11 GPIO_ACTIVE_HIGH>; 104 enable-active-high; 105 vin-supply = <®_can2_en>; 106 }; 107 108 reg_can2_en: regulator-can2-en { 109 compatible = "regulator-fixed"; 110 regulator-name = "can2-en"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 gpio = <&pcal6524_2 13 GPIO_ACTIVE_HIGH>; 114 enable-active-high; 115 }; 116 117 reg_m2_pwr: regulator-m2-pwr { 118 compatible = "regulator-fixed"; 119 regulator-name = "M.2-power"; 120 regulator-min-microvolt = <3300000>; 121 regulator-max-microvolt = <3300000>; 122 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 123 enable-active-high; 124 }; 125 126 reg_usdhc2_vmmc: regulator-usdhc2 { 127 compatible = "regulator-fixed"; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 130 regulator-name = "VSD_3V3"; 131 regulator-min-microvolt = <3300000>; 132 regulator-max-microvolt = <3300000>; 133 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 134 enable-active-high; 135 off-on-delay-us = <12000>; 136 }; 137 138 reg_usdhc3_vmmc: regulator-usdhc3 { 139 compatible = "regulator-fixed"; 140 regulator-name = "WLAN_EN"; 141 regulator-min-microvolt = <3300000>; 142 regulator-max-microvolt = <3300000>; 143 vin-supply = <®_m2_pwr>; 144 gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; 145 /* 146 * IW612 wifi chip needs more delay than other wifi chips to complete 147 * the host interface initialization after power up, otherwise the 148 * internal state of IW612 may be unstable, resulting in the failure of 149 * the SDIO3.0 switch voltage. 150 */ 151 startup-delay-us = <20000>; 152 enable-active-high; 153 }; 154 155 reg_vdd_12v: regulator-vdd-12v { 156 compatible = "regulator-fixed"; 157 regulator-name = "reg_vdd_12v"; 158 regulator-min-microvolt = <12000000>; 159 regulator-max-microvolt = <12000000>; 160 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; 161 enable-active-high; 162 }; 163 164 reg_vref_1v8: regulator-adc-vref { 165 compatible = "regulator-fixed"; 166 regulator-name = "vref_1v8"; 167 regulator-min-microvolt = <1800000>; 168 regulator-max-microvolt = <1800000>; 169 }; 170 171 usdhc3_pwrseq: usdhc3_pwrseq { 172 compatible = "mmc-pwrseq-simple"; 173 reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; 174 }; 175}; 176 177&adc1 { 178 vref-supply = <®_vref_1v8>; 179 status = "okay"; 180}; 181 182&cm33 { 183 mbox-names = "tx", "rx", "rxdb"; 184 mboxes = <&mu1 0 1>, 185 <&mu1 1 1>, 186 <&mu1 3 1>; 187 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 188 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 189 status = "okay"; 190}; 191 192&fec { 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_fec>; 195 phy-mode = "rgmii-id"; 196 phy-handle = <ðphy2>; 197 fsl,magic-packet; 198 status = "okay"; 199 200 mdio { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 clock-frequency = <5000000>; 204 205 ethphy2: ethernet-phy@2 { 206 compatible = "ethernet-phy-ieee802.3-c22"; 207 reg = <2>; 208 eee-broken-1000t; 209 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 210 reset-assert-us = <10000>; 211 reset-deassert-us = <80000>; 212 realtek,clkout-disable; 213 }; 214 }; 215}; 216 217&flexcan1 { 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_flexcan1>; 220 xceiver-supply = <®_can1_stby>; 221 status = "okay"; 222}; 223 224&flexcan2 { 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_flexcan2>; 227 xceiver-supply = <®_can2_stby>; 228 status = "okay"; 229}; 230 231&lpi2c1 { 232 clock-frequency = <400000>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_lpi2c1>; 235 status = "okay"; 236 237 lsm6dsm@6a { 238 compatible = "st,lsm6dso"; 239 reg = <0x6a>; 240 }; 241}; 242 243&lpi2c2 { 244 clock-frequency = <400000>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_lpi2c2>; 247 status = "okay"; 248 249 pcal6524_2: gpio@20 { 250 compatible = "nxp,pcal6524"; 251 reg = <0x20>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 }; 255 256 pcal6524: gpio@22 { 257 compatible = "nxp,pcal6524"; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_pcal6524>; 260 reg = <0x22>; 261 gpio-controller; 262 #gpio-cells = <2>; 263 interrupt-controller; 264 #interrupt-cells = <2>; 265 interrupt-parent = <&gpio3>; 266 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 267 }; 268 269 pmic@25 { 270 compatible = "nxp,pca9452"; 271 reg = <0x25>; 272 interrupt-parent = <&pcal6524>; 273 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 274 275 regulators { 276 buck1: BUCK1 { 277 regulator-name = "BUCK1"; 278 regulator-min-microvolt = <610000>; 279 regulator-max-microvolt = <950000>; 280 regulator-boot-on; 281 regulator-always-on; 282 regulator-ramp-delay = <3125>; 283 }; 284 285 buck2: BUCK2 { 286 regulator-name = "BUCK2"; 287 regulator-min-microvolt = <600000>; 288 regulator-max-microvolt = <670000>; 289 regulator-boot-on; 290 regulator-always-on; 291 regulator-ramp-delay = <3125>; 292 }; 293 294 buck4: BUCK4 { 295 regulator-name = "BUCK4"; 296 regulator-min-microvolt = <1620000>; 297 regulator-max-microvolt = <3400000>; 298 regulator-boot-on; 299 regulator-always-on; 300 }; 301 302 buck5: BUCK5 { 303 regulator-name = "BUCK5"; 304 regulator-min-microvolt = <1620000>; 305 regulator-max-microvolt = <3400000>; 306 regulator-boot-on; 307 regulator-always-on; 308 }; 309 310 buck6: BUCK6 { 311 regulator-name = "BUCK6"; 312 regulator-min-microvolt = <1060000>; 313 regulator-max-microvolt = <1140000>; 314 regulator-boot-on; 315 regulator-always-on; 316 }; 317 318 ldo1: LDO1 { 319 regulator-name = "LDO1"; 320 regulator-min-microvolt = <1620000>; 321 regulator-max-microvolt = <1980000>; 322 regulator-boot-on; 323 regulator-always-on; 324 }; 325 326 ldo3: LDO3 { 327 regulator-name = "LDO3"; 328 regulator-min-microvolt = <1710000>; 329 regulator-max-microvolt = <1890000>; 330 regulator-boot-on; 331 regulator-always-on; 332 }; 333 334 ldo4: LDO4 { 335 regulator-name = "LDO4"; 336 regulator-min-microvolt = <800000>; 337 regulator-max-microvolt = <840000>; 338 regulator-boot-on; 339 regulator-always-on; 340 }; 341 342 ldo5: LDO5 { 343 regulator-name = "LDO5"; 344 regulator-min-microvolt = <1800000>; 345 regulator-max-microvolt = <3300000>; 346 regulator-boot-on; 347 regulator-always-on; 348 }; 349 }; 350 }; 351}; 352 353&lpi2c3 { 354 clock-frequency = <400000>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&pinctrl_lpi2c3>; 357 status = "okay"; 358}; 359 360&lpuart1 { /* console */ 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_uart1>; 363 status = "okay"; 364}; 365 366&mu1 { 367 status = "okay"; 368}; 369 370&mu2 { 371 status = "okay"; 372}; 373 374&usbotg1 { 375 dr_mode = "otg"; 376 hnp-disable; 377 srp-disable; 378 adp-disable; 379 disable-over-current; 380 samsung,picophy-pre-emp-curr-control = <3>; 381 samsung,picophy-dc-vol-level-adjust = <7>; 382 status = "okay"; 383}; 384 385&usbotg2 { 386 dr_mode = "host"; 387 disable-over-current; 388 samsung,picophy-pre-emp-curr-control = <3>; 389 samsung,picophy-dc-vol-level-adjust = <7>; 390 status = "okay"; 391}; 392 393&usdhc1 { 394 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 395 pinctrl-0 = <&pinctrl_usdhc1>; 396 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 397 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 398 bus-width = <8>; 399 non-removable; 400 status = "okay"; 401}; 402 403&usdhc2 { 404 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 405 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 406 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 407 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 408 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 409 vmmc-supply = <®_usdhc2_vmmc>; 410 bus-width = <4>; 411 no-mmc; 412 status = "okay"; 413}; 414 415&usdhc3 { 416 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 417 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; 418 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; 419 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; 420 pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; 421 mmc-pwrseq = <&usdhc3_pwrseq>; 422 vmmc-supply = <®_usdhc3_vmmc>; 423 bus-width = <4>; 424 keep-power-in-suspend; 425 non-removable; 426 wakeup-source; 427 status = "okay"; 428}; 429 430&wdog3 { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_wdog>; 433 fsl,ext-reset-output; 434 status = "okay"; 435}; 436 437&iomuxc { 438 pinctrl_flexcan1: flexcan1grp { 439 fsl,pins = < 440 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 441 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 442 >; 443 }; 444 445 pinctrl_flexcan2: flexcan2grp { 446 fsl,pins = < 447 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 448 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 449 >; 450 }; 451 452 pinctrl_lpi2c1: lpi2c1grp { 453 fsl,pins = < 454 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 455 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 456 >; 457 }; 458 459 pinctrl_lpi2c2: lpi2c2grp { 460 fsl,pins = < 461 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 462 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 463 >; 464 }; 465 466 pinctrl_lpi2c3: lpi2c3grp { 467 fsl,pins = < 468 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 469 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 470 >; 471 }; 472 473 pinctrl_pcal6524: pcal6524grp { 474 fsl,pins = < 475 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 476 >; 477 }; 478 479 pinctrl_fec: fecgrp { 480 fsl,pins = < 481 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 482 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 483 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 484 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 485 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 486 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 487 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e 488 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 489 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 490 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 491 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 492 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 493 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 494 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 495 >; 496 }; 497 498 pinctrl_uart1: uart1grp { 499 fsl,pins = < 500 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 501 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 502 >; 503 }; 504 505 pinctrl_uart5: uart5grp { 506 fsl,pins = < 507 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 508 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 509 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 510 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 511 >; 512 }; 513 514 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 515 pinctrl_usdhc1: usdhc1grp { 516 fsl,pins = < 517 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 518 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 519 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 520 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 521 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 522 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 523 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 524 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 525 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 526 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 527 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 528 >; 529 }; 530 531 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 532 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 533 fsl,pins = < 534 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 535 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 536 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 537 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 538 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 539 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 540 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 541 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 542 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 543 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 544 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 545 >; 546 }; 547 548 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 549 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 550 fsl,pins = < 551 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 552 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 553 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 554 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 555 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 556 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 557 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 558 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 559 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 560 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 561 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 562 >; 563 }; 564 565 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 566 fsl,pins = < 567 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 568 >; 569 }; 570 571 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 572 fsl,pins = < 573 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 574 >; 575 }; 576 577 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 578 pinctrl_usdhc2: usdhc2grp { 579 fsl,pins = < 580 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 581 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 582 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 583 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 584 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 585 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 586 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 587 >; 588 }; 589 590 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 591 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 592 fsl,pins = < 593 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 594 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 595 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 596 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 597 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 598 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 599 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 600 >; 601 }; 602 603 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 604 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 605 fsl,pins = < 606 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 607 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 608 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 609 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 610 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 611 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 612 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 613 >; 614 }; 615 616 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 617 pinctrl_usdhc3: usdhc3grp { 618 fsl,pins = < 619 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 620 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 621 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 622 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 623 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 624 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 625 >; 626 }; 627 628 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 629 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 630 fsl,pins = < 631 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e 632 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e 633 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 634 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 635 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 636 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 637 >; 638 }; 639 640 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 641 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 642 fsl,pins = < 643 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe 644 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe 645 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe 646 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe 647 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe 648 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe 649 >; 650 }; 651 652 pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { 653 fsl,pins = < 654 MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e 655 MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e 656 MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e 657 MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e 658 MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e 659 MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e 660 >; 661 }; 662 663 pinctrl_usdhc3_wlan: usdhc3wlangrp { 664 fsl,pins = < 665 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 666 >; 667 }; 668 669 pinctrl_wdog: wdoggrp { 670 fsl,pins = < 671 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 672 >; 673 }; 674}; 675