1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 11X11 EVK board"; 13 compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 14 15 chosen { 16 stdout-path = &lpuart1; 17 }; 18 19 reserved-memory { 20 #address-cells = <2>; 21 #size-cells = <2>; 22 ranges; 23 24 linux,cma { 25 compatible = "shared-dma-pool"; 26 reusable; 27 alloc-ranges = <0 0x80000000 0 0x40000000>; 28 size = <0 0x10000000>; 29 linux,cma-default; 30 }; 31 32 vdev0vring0: vdev0vring0@a4000000 { 33 reg = <0 0xa4000000 0 0x8000>; 34 no-map; 35 }; 36 37 vdev0vring1: vdev0vring1@a4008000 { 38 reg = <0 0xa4008000 0 0x8000>; 39 no-map; 40 }; 41 42 vdev1vring0: vdev1vring0@a4010000 { 43 reg = <0 0xa4010000 0 0x8000>; 44 no-map; 45 }; 46 47 vdev1vring1: vdev1vring1@a4018000 { 48 reg = <0 0xa4018000 0 0x8000>; 49 no-map; 50 }; 51 52 rsc_table: rsc-table@2021e000 { 53 reg = <0 0x2021e000 0 0x1000>; 54 no-map; 55 }; 56 57 vdevbuffer: vdevbuffer@a4020000 { 58 compatible = "shared-dma-pool"; 59 reg = <0 0xa4020000 0 0x100000>; 60 no-map; 61 }; 62 63 }; 64 65 reg_vdd_12v: regulator-vdd-12v { 66 compatible = "regulator-fixed"; 67 regulator-name = "VDD_12V"; 68 regulator-min-microvolt = <12000000>; 69 regulator-max-microvolt = <12000000>; 70 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; 71 enable-active-high; 72 }; 73 74 reg_vref_1v8: regulator-adc-vref { 75 compatible = "regulator-fixed"; 76 regulator-name = "vref_1v8"; 77 regulator-min-microvolt = <1800000>; 78 regulator-max-microvolt = <1800000>; 79 }; 80 81 reg_audio_pwr: regulator-audio-pwr { 82 compatible = "regulator-fixed"; 83 regulator-name = "audio-pwr"; 84 regulator-min-microvolt = <3300000>; 85 regulator-max-microvolt = <3300000>; 86 gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; 87 enable-active-high; 88 }; 89 90 reg_can2_standby: regulator-can2-standby { 91 compatible = "regulator-fixed"; 92 regulator-name = "can2-stby"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 gpio = <&adp5585 6 GPIO_ACTIVE_LOW>; 96 }; 97 98 reg_usdhc2_vmmc: regulator-usdhc2 { 99 compatible = "regulator-fixed"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 102 regulator-name = "VSD_3V3"; 103 regulator-min-microvolt = <3300000>; 104 regulator-max-microvolt = <3300000>; 105 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 106 off-on-delay-us = <12000>; 107 enable-active-high; 108 }; 109 110 backlight_lvds: backlight-lvds { 111 compatible = "pwm-backlight"; 112 pwms = <&adp5585 0 100000 0>; 113 brightness-levels = <0 100>; 114 num-interpolated-steps = <100>; 115 default-brightness-level = <100>; 116 power-supply = <®_vdd_12v>; 117 enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>; 118 status = "disabled"; 119 }; 120 121 bt_sco_codec: bt-sco-codec { 122 compatible = "linux,bt-sco"; 123 #sound-dai-cells = <1>; 124 }; 125 126 sound-bt-sco { 127 compatible = "simple-audio-card"; 128 simple-audio-card,name = "bt-sco-audio"; 129 simple-audio-card,format = "dsp_a"; 130 simple-audio-card,bitclock-inversion; 131 simple-audio-card,frame-master = <&btcpu>; 132 simple-audio-card,bitclock-master = <&btcpu>; 133 134 btcpu: simple-audio-card,cpu { 135 sound-dai = <&sai1>; 136 dai-tdm-slot-num = <2>; 137 dai-tdm-slot-width = <16>; 138 }; 139 140 simple-audio-card,codec { 141 sound-dai = <&bt_sco_codec 1>; 142 }; 143 }; 144 145 sound-micfil { 146 compatible = "fsl,imx-audio-card"; 147 model = "micfil-audio"; 148 149 pri-dai-link { 150 link-name = "micfil hifi"; 151 format = "i2s"; 152 153 cpu { 154 sound-dai = <&micfil>; 155 }; 156 }; 157 }; 158 159 sound-wm8962 { 160 compatible = "fsl,imx-audio-wm8962"; 161 model = "wm8962-audio"; 162 audio-cpu = <&sai3>; 163 audio-codec = <&wm8962>; 164 hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 165 audio-routing = 166 "Headphone Jack", "HPOUTL", 167 "Headphone Jack", "HPOUTR", 168 "Ext Spk", "SPKOUTL", 169 "Ext Spk", "SPKOUTR", 170 "AMIC", "MICBIAS", 171 "IN3R", "AMIC", 172 "IN1R", "AMIC"; 173 }; 174 175 sound-xcvr { 176 compatible = "fsl,imx-audio-card"; 177 model = "imx-audio-xcvr"; 178 179 pri-dai-link { 180 link-name = "XCVR PCM"; 181 182 cpu { 183 sound-dai = <&xcvr>; 184 }; 185 }; 186 }; 187}; 188 189&adc1 { 190 vref-supply = <®_vref_1v8>; 191 status = "okay"; 192}; 193 194&cm33 { 195 mbox-names = "tx", "rx", "rxdb"; 196 mboxes = <&mu1 0 1>, 197 <&mu1 1 1>, 198 <&mu1 3 1>; 199 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 200 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 201 status = "okay"; 202}; 203 204&eqos { 205 pinctrl-names = "default", "sleep"; 206 pinctrl-0 = <&pinctrl_eqos>; 207 pinctrl-1 = <&pinctrl_eqos_sleep>; 208 phy-mode = "rgmii-id"; 209 phy-handle = <ðphy1>; 210 status = "okay"; 211 212 mdio { 213 compatible = "snps,dwmac-mdio"; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 clock-frequency = <5000000>; 217 218 ethphy1: ethernet-phy@1 { 219 reg = <1>; 220 eee-broken-1000t; 221 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 222 reset-assert-us = <10000>; 223 reset-deassert-us = <80000>; 224 }; 225 }; 226}; 227 228&fec { 229 pinctrl-names = "default", "sleep"; 230 pinctrl-0 = <&pinctrl_fec>; 231 pinctrl-1 = <&pinctrl_fec_sleep>; 232 phy-mode = "rgmii-id"; 233 phy-handle = <ðphy2>; 234 fsl,magic-packet; 235 status = "okay"; 236 237 mdio { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 clock-frequency = <5000000>; 241 242 ethphy2: ethernet-phy@2 { 243 reg = <2>; 244 eee-broken-1000t; 245 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 246 reset-assert-us = <10000>; 247 reset-deassert-us = <80000>; 248 }; 249 }; 250}; 251 252&flexcan2 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_flexcan2>; 255 xceiver-supply = <®_can2_standby>; 256 status = "okay"; 257}; 258 259&lpi2c1 { 260 clock-frequency = <400000>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_lpi2c1>; 263 status = "okay"; 264 265 wm8962: codec@1a { 266 compatible = "wlf,wm8962"; 267 reg = <0x1a>; 268 clocks = <&clk IMX93_CLK_SAI3_GATE>; 269 DCVDD-supply = <®_audio_pwr>; 270 DBVDD-supply = <®_audio_pwr>; 271 AVDD-supply = <®_audio_pwr>; 272 CPVDD-supply = <®_audio_pwr>; 273 MICVDD-supply = <®_audio_pwr>; 274 PLLVDD-supply = <®_audio_pwr>; 275 SPKVDD1-supply = <®_audio_pwr>; 276 SPKVDD2-supply = <®_audio_pwr>; 277 gpio-cfg = < 278 0x0000 /* 0:Default */ 279 0x0000 /* 1:Default */ 280 0x0000 /* 2:FN_DMICCLK */ 281 0x0000 /* 3:Default */ 282 0x0000 /* 4:FN_DMICCDAT */ 283 0x0000 /* 5:Default */ 284 >; 285 }; 286 287 inertial-meter@6a { 288 compatible = "st,lsm6dso"; 289 reg = <0x6a>; 290 }; 291}; 292 293&lpi2c2 { 294 clock-frequency = <400000>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_lpi2c2>; 297 status = "okay"; 298 299 pcal6524: gpio@22 { 300 compatible = "nxp,pcal6524"; 301 reg = <0x22>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_pcal6524>; 304 gpio-controller; 305 #gpio-cells = <2>; 306 interrupt-controller; 307 #interrupt-cells = <2>; 308 interrupt-parent = <&gpio3>; 309 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 310 }; 311 312 pmic@25 { 313 compatible = "nxp,pca9451a"; 314 reg = <0x25>; 315 interrupt-parent = <&pcal6524>; 316 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 317 318 regulators { 319 buck1: BUCK1 { 320 regulator-name = "BUCK1"; 321 regulator-min-microvolt = <610000>; 322 regulator-max-microvolt = <950000>; 323 regulator-boot-on; 324 regulator-always-on; 325 regulator-ramp-delay = <3125>; 326 }; 327 328 buck2: BUCK2 { 329 regulator-name = "BUCK2"; 330 regulator-min-microvolt = <600000>; 331 regulator-max-microvolt = <670000>; 332 regulator-boot-on; 333 regulator-always-on; 334 regulator-ramp-delay = <3125>; 335 }; 336 337 buck4: BUCK4 { 338 regulator-name = "BUCK4"; 339 regulator-min-microvolt = <1620000>; 340 regulator-max-microvolt = <3400000>; 341 regulator-boot-on; 342 regulator-always-on; 343 }; 344 345 buck5: BUCK5 { 346 regulator-name = "BUCK5"; 347 regulator-min-microvolt = <1620000>; 348 regulator-max-microvolt = <3400000>; 349 regulator-boot-on; 350 regulator-always-on; 351 }; 352 353 buck6: BUCK6 { 354 regulator-name = "BUCK6"; 355 regulator-min-microvolt = <1060000>; 356 regulator-max-microvolt = <1140000>; 357 regulator-boot-on; 358 regulator-always-on; 359 }; 360 361 ldo1: LDO1 { 362 regulator-name = "LDO1"; 363 regulator-min-microvolt = <1620000>; 364 regulator-max-microvolt = <1980000>; 365 regulator-boot-on; 366 regulator-always-on; 367 }; 368 369 ldo4: LDO4 { 370 regulator-name = "LDO4"; 371 regulator-min-microvolt = <800000>; 372 regulator-max-microvolt = <840000>; 373 regulator-boot-on; 374 regulator-always-on; 375 }; 376 377 ldo5: LDO5 { 378 regulator-name = "LDO5"; 379 regulator-min-microvolt = <1800000>; 380 regulator-max-microvolt = <3300000>; 381 regulator-boot-on; 382 regulator-always-on; 383 }; 384 }; 385 }; 386 387 adp5585: io-expander@34 { 388 compatible = "adi,adp5585-00", "adi,adp5585"; 389 reg = <0x34>; 390 vdd-supply = <&buck4>; 391 gpio-controller; 392 #gpio-cells = <2>; 393 gpio-reserved-ranges = <5 1>; 394 #pwm-cells = <3>; 395 }; 396}; 397 398&lpi2c3 { 399 clock-frequency = <400000>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_lpi2c3>; 402 status = "okay"; 403 404 adp5585_isp: io-expander@34 { 405 compatible = "adi,adp5585-01", "adi,adp5585"; 406 reg = <0x34>; 407 gpio-controller; 408 #gpio-cells = <2>; 409 #pwm-cells = <3>; 410 }; 411 412 ptn5110: tcpc@50 { 413 compatible = "nxp,ptn5110", "tcpci"; 414 reg = <0x50>; 415 interrupt-parent = <&gpio3>; 416 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 417 418 typec1_con: connector { 419 compatible = "usb-c-connector"; 420 label = "USB-C"; 421 power-role = "dual"; 422 data-role = "dual"; 423 try-power-role = "sink"; 424 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 425 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 426 PDO_VAR(5000, 20000, 3000)>; 427 op-sink-microwatt = <15000000>; 428 self-powered; 429 430 ports { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 port@0 { 435 reg = <0>; 436 437 typec1_dr_sw: endpoint { 438 remote-endpoint = <&usb1_drd_sw>; 439 }; 440 }; 441 }; 442 }; 443 }; 444 445 ptn5110_2: tcpc@51 { 446 compatible = "nxp,ptn5110", "tcpci"; 447 reg = <0x51>; 448 interrupt-parent = <&gpio3>; 449 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 450 451 typec2_con: connector { 452 compatible = "usb-c-connector"; 453 label = "USB-C"; 454 power-role = "dual"; 455 data-role = "dual"; 456 try-power-role = "sink"; 457 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 458 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 459 PDO_VAR(5000, 20000, 3000)>; 460 op-sink-microwatt = <15000000>; 461 self-powered; 462 463 ports { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 467 port@0 { 468 reg = <0>; 469 470 typec2_dr_sw: endpoint { 471 remote-endpoint = <&usb2_drd_sw>; 472 }; 473 }; 474 }; 475 }; 476 }; 477 478 pcf2131: rtc@53 { 479 compatible = "nxp,pcf2131"; 480 reg = <0x53>; 481 interrupt-parent = <&pcal6524>; 482 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 483 }; 484}; 485 486&lpuart1 { /* console */ 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pinctrl_uart1>; 489 status = "okay"; 490}; 491 492&lpuart5 { 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_uart5>; 495 status = "okay"; 496}; 497 498&micfil { 499 pinctrl-names = "default", "sleep"; 500 pinctrl-0 = <&pinctrl_pdm>; 501 pinctrl-1 = <&pinctrl_pdm_sleep>; 502 assigned-clocks = <&clk IMX93_CLK_PDM>; 503 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 504 assigned-clock-rates = <49152000>; 505 status = "okay"; 506}; 507 508&mu1 { 509 status = "okay"; 510}; 511 512&mu2 { 513 status = "okay"; 514}; 515 516&sai1 { 517 pinctrl-names = "default", "sleep"; 518 pinctrl-0 = <&pinctrl_sai1>; 519 pinctrl-1 = <&pinctrl_sai1_sleep>; 520 assigned-clocks = <&clk IMX93_CLK_SAI1>; 521 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 522 assigned-clock-rates = <12288000>; 523 fsl,sai-mclk-direction-output; 524 status = "okay"; 525}; 526 527&sai3 { 528 pinctrl-names = "default", "sleep"; 529 pinctrl-0 = <&pinctrl_sai3>; 530 pinctrl-1 = <&pinctrl_sai3_sleep>; 531 assigned-clocks = <&clk IMX93_CLK_SAI3>; 532 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 533 assigned-clock-rates = <12288000>; 534 fsl,sai-mclk-direction-output; 535 status = "okay"; 536}; 537 538&usbotg1 { 539 dr_mode = "otg"; 540 hnp-disable; 541 srp-disable; 542 adp-disable; 543 usb-role-switch; 544 disable-over-current; 545 samsung,picophy-pre-emp-curr-control = <3>; 546 samsung,picophy-dc-vol-level-adjust = <7>; 547 status = "okay"; 548 549 port { 550 usb1_drd_sw: endpoint { 551 remote-endpoint = <&typec1_dr_sw>; 552 }; 553 }; 554}; 555 556&usbotg2 { 557 dr_mode = "otg"; 558 hnp-disable; 559 srp-disable; 560 adp-disable; 561 usb-role-switch; 562 disable-over-current; 563 samsung,picophy-pre-emp-curr-control = <3>; 564 samsung,picophy-dc-vol-level-adjust = <7>; 565 status = "okay"; 566 567 port { 568 usb2_drd_sw: endpoint { 569 remote-endpoint = <&typec2_dr_sw>; 570 }; 571 }; 572}; 573 574&usdhc1 { 575 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 576 pinctrl-0 = <&pinctrl_usdhc1>; 577 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 578 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 579 bus-width = <8>; 580 non-removable; 581 status = "okay"; 582}; 583 584&usdhc2 { 585 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 586 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 587 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 588 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 589 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 590 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 591 vmmc-supply = <®_usdhc2_vmmc>; 592 bus-width = <4>; 593 status = "okay"; 594 no-mmc; 595}; 596 597&wdog3 { 598 status = "okay"; 599}; 600 601&xcvr { 602 pinctrl-names = "default", "sleep"; 603 pinctrl-0 = <&pinctrl_spdif>; 604 pinctrl-1 = <&pinctrl_spdif_sleep>; 605 assigned-clocks = <&clk IMX93_CLK_SPDIF>, 606 <&clk IMX93_CLK_AUDIO_XCVR>; 607 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, 608 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 609 assigned-clock-rates = <12288000>, <200000000>; 610 status = "okay"; 611}; 612 613&iomuxc { 614 pinctrl_eqos: eqosgrp { 615 fsl,pins = < 616 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 617 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 618 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 619 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 620 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 621 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 622 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 623 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 624 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 625 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 626 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 627 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 628 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 629 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 630 >; 631 }; 632 633 pinctrl_eqos_sleep: eqossleepgrp { 634 fsl,pins = < 635 MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e 636 MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e 637 MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e 638 MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e 639 MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e 640 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e 641 MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e 642 MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e 643 MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e 644 MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e 645 MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e 646 MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e 647 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e 648 MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e 649 >; 650 }; 651 652 pinctrl_fec: fecgrp { 653 fsl,pins = < 654 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 655 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 656 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 657 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 658 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 659 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 660 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 661 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 662 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 663 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 664 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 665 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 666 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe 667 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 668 >; 669 }; 670 671 pinctrl_lpi2c3: lpi2c3grp { 672 fsl,pins = < 673 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 674 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 675 >; 676 }; 677 678 pinctrl_fec_sleep: fecsleepgrp { 679 fsl,pins = < 680 MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e 681 MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 682 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e 683 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e 684 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e 685 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e 686 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 687 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 688 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e 689 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e 690 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e 691 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e 692 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e 693 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 694 >; 695 }; 696 697 pinctrl_flexcan2: flexcan2grp { 698 fsl,pins = < 699 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 700 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 701 >; 702 }; 703 704 pinctrl_uart1: uart1grp { 705 fsl,pins = < 706 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 707 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 708 >; 709 }; 710 711 pinctrl_uart5: uart5grp { 712 fsl,pins = < 713 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 714 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 715 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 716 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 717 >; 718 }; 719 720 pinctrl_lpi2c1: lpi2c1grp { 721 fsl,pins = < 722 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 723 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 724 >; 725 }; 726 727 pinctrl_lpi2c2: lpi2c2grp { 728 fsl,pins = < 729 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 730 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 731 >; 732 }; 733 734 pinctrl_lpi2c3: lpi2c3grp { 735 fsl,pins = < 736 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 737 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 738 >; 739 }; 740 741 pinctrl_pcal6524: pcal6524grp { 742 fsl,pins = < 743 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 744 >; 745 }; 746 747 pinctrl_pdm: pdmgrp { 748 fsl,pins = < 749 MX93_PAD_PDM_CLK__PDM_CLK 0x31e 750 MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e 751 MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e 752 >; 753 }; 754 755 pinctrl_pdm_sleep: pdmsleepgrp { 756 fsl,pins = < 757 MX93_PAD_PDM_CLK__GPIO1_IO08 0x31e 758 MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x31e 759 MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e 760 >; 761 }; 762 763 pinctrl_sai1: sai1grp { 764 fsl,pins = < 765 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 766 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 767 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e 768 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e 769 >; 770 }; 771 772 pinctrl_sai1_sleep: sai1sleepgrp { 773 fsl,pins = < 774 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x51e 775 MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x51e 776 MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x51e 777 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e 778 >; 779 }; 780 781 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 782 pinctrl_usdhc1: usdhc1grp { 783 fsl,pins = < 784 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 785 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 786 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 787 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 788 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 789 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 790 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 791 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 792 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 793 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 794 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 795 >; 796 }; 797 798 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 799 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 800 fsl,pins = < 801 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 802 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 803 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 804 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 805 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 806 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 807 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 808 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 809 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 810 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 811 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 812 >; 813 }; 814 815 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 816 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 817 fsl,pins = < 818 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 819 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 820 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 821 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 822 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 823 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 824 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 825 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 826 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 827 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 828 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 829 >; 830 }; 831 832 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 833 fsl,pins = < 834 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 835 >; 836 }; 837 838 pinctrl_sai3: sai3grp { 839 fsl,pins = < 840 MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 841 MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 842 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e 843 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e 844 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e 845 >; 846 }; 847 848 pinctrl_sai3_sleep: sai3sleepgrp { 849 fsl,pins = < 850 MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e 851 MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e 852 MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e 853 MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e 854 MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e 855 >; 856 }; 857 858 pinctrl_spdif: spdifgrp { 859 fsl,pins = < 860 MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e 861 MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e 862 >; 863 }; 864 865 pinctrl_spdif_sleep: spdifsleepgrp { 866 fsl,pins = < 867 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e 868 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e 869 >; 870 }; 871 872 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 873 fsl,pins = < 874 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 875 >; 876 }; 877 878 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 879 fsl,pins = < 880 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e 881 >; 882 }; 883 884 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 885 pinctrl_usdhc2: usdhc2grp { 886 fsl,pins = < 887 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 888 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 889 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 890 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 891 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 892 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 893 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 894 >; 895 }; 896 897 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 898 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 899 fsl,pins = < 900 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 901 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 902 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 903 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 904 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 905 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 906 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 907 >; 908 }; 909 910 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 911 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 912 fsl,pins = < 913 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 914 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 915 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 916 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 917 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 918 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 919 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 920 >; 921 }; 922 923 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 924 fsl,pins = < 925 MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e 926 MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e 927 MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e 928 MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e 929 MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e 930 MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e 931 MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 932 >; 933 }; 934 935}; 936