1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 11X11 EVK board"; 13 compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 14 15 aliases { 16 ethernet0 = &fec; 17 ethernet1 = &eqos; 18 gpio0 = &gpio1; 19 gpio1 = &gpio2; 20 gpio2 = &gpio3; 21 i2c0 = &lpi2c1; 22 i2c1 = &lpi2c2; 23 i2c2 = &lpi2c3; 24 mmc0 = &usdhc1; 25 mmc1 = &usdhc2; 26 rtc0 = &bbnsm_rtc; 27 serial0 = &lpuart1; 28 serial1 = &lpuart2; 29 serial2 = &lpuart3; 30 serial3 = &lpuart4; 31 serial4 = &lpuart5; 32 }; 33 34 chosen { 35 stdout-path = &lpuart1; 36 }; 37 38 reserved-memory { 39 #address-cells = <2>; 40 #size-cells = <2>; 41 ranges; 42 43 linux,cma { 44 compatible = "shared-dma-pool"; 45 reusable; 46 alloc-ranges = <0 0x80000000 0 0x40000000>; 47 size = <0 0x10000000>; 48 linux,cma-default; 49 }; 50 51 vdev0vring0: vdev0vring0@a4000000 { 52 reg = <0 0xa4000000 0 0x8000>; 53 no-map; 54 }; 55 56 vdev0vring1: vdev0vring1@a4008000 { 57 reg = <0 0xa4008000 0 0x8000>; 58 no-map; 59 }; 60 61 vdev1vring0: vdev1vring0@a4010000 { 62 reg = <0 0xa4010000 0 0x8000>; 63 no-map; 64 }; 65 66 vdev1vring1: vdev1vring1@a4018000 { 67 reg = <0 0xa4018000 0 0x8000>; 68 no-map; 69 }; 70 71 rsc_table: rsc-table@2021e000 { 72 reg = <0 0x2021e000 0 0x1000>; 73 no-map; 74 }; 75 76 vdevbuffer: vdevbuffer@a4020000 { 77 compatible = "shared-dma-pool"; 78 reg = <0 0xa4020000 0 0x100000>; 79 no-map; 80 }; 81 82 }; 83 84 reg_vdd_12v: regulator-vdd-12v { 85 compatible = "regulator-fixed"; 86 regulator-name = "VDD_12V"; 87 regulator-min-microvolt = <12000000>; 88 regulator-max-microvolt = <12000000>; 89 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; 90 enable-active-high; 91 }; 92 93 reg_vref_1v8: regulator-adc-vref { 94 compatible = "regulator-fixed"; 95 regulator-name = "vref_1v8"; 96 regulator-min-microvolt = <1800000>; 97 regulator-max-microvolt = <1800000>; 98 }; 99 100 reg_audio_pwr: regulator-audio-pwr { 101 compatible = "regulator-fixed"; 102 regulator-name = "audio-pwr"; 103 regulator-min-microvolt = <3300000>; 104 regulator-max-microvolt = <3300000>; 105 gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; 106 enable-active-high; 107 }; 108 109 reg_can2_standby: regulator-can2-standby { 110 compatible = "regulator-fixed"; 111 regulator-name = "can2-stby"; 112 regulator-min-microvolt = <3300000>; 113 regulator-max-microvolt = <3300000>; 114 gpio = <&adp5585 6 GPIO_ACTIVE_LOW>; 115 }; 116 117 reg_m2_pwr: regulator-m2-pwr { 118 compatible = "regulator-fixed"; 119 regulator-name = "M.2-power"; 120 regulator-min-microvolt = <3300000>; 121 regulator-max-microvolt = <3300000>; 122 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 123 enable-active-high; 124 }; 125 126 reg_usdhc2_vmmc: regulator-usdhc2 { 127 compatible = "regulator-fixed"; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 130 regulator-name = "VSD_3V3"; 131 regulator-min-microvolt = <3300000>; 132 regulator-max-microvolt = <3300000>; 133 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 134 off-on-delay-us = <12000>; 135 enable-active-high; 136 }; 137 138 reg_usdhc3_vmmc: regulator-usdhc3 { 139 compatible = "regulator-fixed"; 140 regulator-name = "WLAN_EN"; 141 regulator-min-microvolt = <3300000>; 142 regulator-max-microvolt = <3300000>; 143 vin-supply = <®_m2_pwr>; 144 gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; 145 /* 146 * IW612 wifi chip needs more delay than other wifi chips to complete 147 * the host interface initialization after power up, otherwise the 148 * internal state of IW612 may be unstable, resulting in the failure of 149 * the SDIO3.0 switch voltage. 150 */ 151 startup-delay-us = <20000>; 152 enable-active-high; 153 }; 154 155 usdhc3_pwrseq: usdhc3_pwrseq { 156 compatible = "mmc-pwrseq-simple"; 157 reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; 158 }; 159 160 backlight_lvds: backlight-lvds { 161 compatible = "pwm-backlight"; 162 pwms = <&adp5585 0 100000 0>; 163 brightness-levels = <0 100>; 164 num-interpolated-steps = <100>; 165 default-brightness-level = <100>; 166 power-supply = <®_vdd_12v>; 167 enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>; 168 status = "disabled"; 169 }; 170 171 bt_sco_codec: bt-sco-codec { 172 compatible = "linux,bt-sco"; 173 #sound-dai-cells = <1>; 174 }; 175 176 sound-bt-sco { 177 compatible = "simple-audio-card"; 178 simple-audio-card,name = "bt-sco-audio"; 179 simple-audio-card,format = "dsp_a"; 180 simple-audio-card,bitclock-inversion; 181 simple-audio-card,frame-master = <&btcpu>; 182 simple-audio-card,bitclock-master = <&btcpu>; 183 184 btcpu: simple-audio-card,cpu { 185 sound-dai = <&sai1>; 186 dai-tdm-slot-num = <2>; 187 dai-tdm-slot-width = <16>; 188 }; 189 190 simple-audio-card,codec { 191 sound-dai = <&bt_sco_codec 1>; 192 }; 193 }; 194 195 sound-micfil { 196 compatible = "fsl,imx-audio-card"; 197 model = "micfil-audio"; 198 199 pri-dai-link { 200 link-name = "micfil hifi"; 201 format = "i2s"; 202 203 cpu { 204 sound-dai = <&micfil>; 205 }; 206 }; 207 }; 208 209 sound-wm8962 { 210 compatible = "fsl,imx-audio-wm8962"; 211 model = "wm8962-audio"; 212 audio-cpu = <&sai3>; 213 audio-codec = <&wm8962>; 214 hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 215 audio-routing = 216 "Headphone Jack", "HPOUTL", 217 "Headphone Jack", "HPOUTR", 218 "Ext Spk", "SPKOUTL", 219 "Ext Spk", "SPKOUTR", 220 "AMIC", "MICBIAS", 221 "IN3R", "AMIC", 222 "IN1R", "AMIC"; 223 }; 224 225 sound-xcvr { 226 compatible = "fsl,imx-audio-card"; 227 model = "imx-audio-xcvr"; 228 229 pri-dai-link { 230 link-name = "XCVR PCM"; 231 232 cpu { 233 sound-dai = <&xcvr>; 234 }; 235 }; 236 }; 237}; 238 239&adc1 { 240 vref-supply = <®_vref_1v8>; 241 status = "okay"; 242}; 243 244&cm33 { 245 mbox-names = "tx", "rx", "rxdb"; 246 mboxes = <&mu1 0 1>, 247 <&mu1 1 1>, 248 <&mu1 3 1>; 249 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 250 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 251 status = "okay"; 252}; 253 254&eqos { 255 pinctrl-names = "default", "sleep"; 256 pinctrl-0 = <&pinctrl_eqos>; 257 pinctrl-1 = <&pinctrl_eqos_sleep>; 258 phy-mode = "rgmii-id"; 259 phy-handle = <ðphy1>; 260 status = "okay"; 261 262 mdio { 263 compatible = "snps,dwmac-mdio"; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 clock-frequency = <5000000>; 267 268 ethphy1: ethernet-phy@1 { 269 reg = <1>; 270 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 271 reset-assert-us = <10000>; 272 reset-deassert-us = <80000>; 273 realtek,clkout-disable; 274 }; 275 }; 276}; 277 278&fec { 279 pinctrl-names = "default", "sleep"; 280 pinctrl-0 = <&pinctrl_fec>; 281 pinctrl-1 = <&pinctrl_fec_sleep>; 282 phy-mode = "rgmii-id"; 283 phy-handle = <ðphy2>; 284 fsl,magic-packet; 285 status = "okay"; 286 287 mdio { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 clock-frequency = <5000000>; 291 292 ethphy2: ethernet-phy@2 { 293 reg = <2>; 294 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 295 reset-assert-us = <10000>; 296 reset-deassert-us = <80000>; 297 realtek,clkout-disable; 298 }; 299 }; 300}; 301 302&flexcan2 { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_flexcan2>; 305 xceiver-supply = <®_can2_standby>; 306 status = "okay"; 307}; 308 309&lpi2c1 { 310 clock-frequency = <400000>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_lpi2c1>; 313 status = "okay"; 314 315 wm8962: codec@1a { 316 compatible = "wlf,wm8962"; 317 reg = <0x1a>; 318 clocks = <&clk IMX93_CLK_SAI3_GATE>; 319 DCVDD-supply = <®_audio_pwr>; 320 DBVDD-supply = <®_audio_pwr>; 321 AVDD-supply = <®_audio_pwr>; 322 CPVDD-supply = <®_audio_pwr>; 323 MICVDD-supply = <®_audio_pwr>; 324 PLLVDD-supply = <®_audio_pwr>; 325 SPKVDD1-supply = <®_audio_pwr>; 326 SPKVDD2-supply = <®_audio_pwr>; 327 gpio-cfg = < 328 0x0000 /* 0:Default */ 329 0x0000 /* 1:Default */ 330 0x0000 /* 2:FN_DMICCLK */ 331 0x0000 /* 3:Default */ 332 0x0000 /* 4:FN_DMICCDAT */ 333 0x0000 /* 5:Default */ 334 >; 335 }; 336 337 inertial-meter@6a { 338 compatible = "st,lsm6dso"; 339 reg = <0x6a>; 340 }; 341}; 342 343&lpi2c2 { 344 clock-frequency = <400000>; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_lpi2c2>; 347 status = "okay"; 348 349 pcal6524: gpio@22 { 350 compatible = "nxp,pcal6524"; 351 reg = <0x22>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_pcal6524>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 interrupt-parent = <&gpio3>; 359 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 360 }; 361 362 pmic@25 { 363 compatible = "nxp,pca9451a"; 364 reg = <0x25>; 365 interrupt-parent = <&pcal6524>; 366 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 367 368 regulators { 369 buck1: BUCK1 { 370 regulator-name = "BUCK1"; 371 regulator-min-microvolt = <610000>; 372 regulator-max-microvolt = <950000>; 373 regulator-boot-on; 374 regulator-always-on; 375 regulator-ramp-delay = <3125>; 376 }; 377 378 buck2: BUCK2 { 379 regulator-name = "BUCK2"; 380 regulator-min-microvolt = <600000>; 381 regulator-max-microvolt = <670000>; 382 regulator-boot-on; 383 regulator-always-on; 384 regulator-ramp-delay = <3125>; 385 }; 386 387 buck4: BUCK4 { 388 regulator-name = "BUCK4"; 389 regulator-min-microvolt = <1620000>; 390 regulator-max-microvolt = <3400000>; 391 regulator-boot-on; 392 regulator-always-on; 393 }; 394 395 buck5: BUCK5 { 396 regulator-name = "BUCK5"; 397 regulator-min-microvolt = <1620000>; 398 regulator-max-microvolt = <3400000>; 399 regulator-boot-on; 400 regulator-always-on; 401 }; 402 403 buck6: BUCK6 { 404 regulator-name = "BUCK6"; 405 regulator-min-microvolt = <1060000>; 406 regulator-max-microvolt = <1140000>; 407 regulator-boot-on; 408 regulator-always-on; 409 }; 410 411 ldo1: LDO1 { 412 regulator-name = "LDO1"; 413 regulator-min-microvolt = <1620000>; 414 regulator-max-microvolt = <1980000>; 415 regulator-boot-on; 416 regulator-always-on; 417 }; 418 419 ldo4: LDO4 { 420 regulator-name = "LDO4"; 421 regulator-min-microvolt = <800000>; 422 regulator-max-microvolt = <840000>; 423 regulator-boot-on; 424 regulator-always-on; 425 }; 426 427 ldo5: LDO5 { 428 regulator-name = "LDO5"; 429 regulator-min-microvolt = <1800000>; 430 regulator-max-microvolt = <3300000>; 431 regulator-boot-on; 432 regulator-always-on; 433 }; 434 }; 435 }; 436 437 adp5585: io-expander@34 { 438 compatible = "adi,adp5585-00", "adi,adp5585"; 439 reg = <0x34>; 440 vdd-supply = <&buck4>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 gpio-reserved-ranges = <5 1>; 444 #pwm-cells = <3>; 445 }; 446}; 447 448&lpi2c3 { 449 clock-frequency = <400000>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_lpi2c3>; 452 status = "okay"; 453 454 adp5585_isp: io-expander@34 { 455 compatible = "adi,adp5585-01", "adi,adp5585"; 456 reg = <0x34>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 #pwm-cells = <3>; 460 }; 461 462 ptn5110: tcpc@50 { 463 compatible = "nxp,ptn5110", "tcpci"; 464 reg = <0x50>; 465 interrupt-parent = <&gpio3>; 466 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 467 468 typec1_con: connector { 469 compatible = "usb-c-connector"; 470 label = "USB-C"; 471 power-role = "dual"; 472 data-role = "dual"; 473 try-power-role = "sink"; 474 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 475 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 476 PDO_VAR(5000, 20000, 3000)>; 477 op-sink-microwatt = <15000000>; 478 self-powered; 479 480 ports { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 484 port@0 { 485 reg = <0>; 486 487 typec1_dr_sw: endpoint { 488 remote-endpoint = <&usb1_drd_sw>; 489 }; 490 }; 491 }; 492 }; 493 }; 494 495 ptn5110_2: tcpc@51 { 496 compatible = "nxp,ptn5110", "tcpci"; 497 reg = <0x51>; 498 interrupt-parent = <&gpio3>; 499 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 500 501 typec2_con: connector { 502 compatible = "usb-c-connector"; 503 label = "USB-C"; 504 power-role = "dual"; 505 data-role = "dual"; 506 try-power-role = "sink"; 507 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 508 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 509 PDO_VAR(5000, 20000, 3000)>; 510 op-sink-microwatt = <15000000>; 511 self-powered; 512 513 ports { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 517 port@0 { 518 reg = <0>; 519 520 typec2_dr_sw: endpoint { 521 remote-endpoint = <&usb2_drd_sw>; 522 }; 523 }; 524 }; 525 }; 526 }; 527 528 pcf2131: rtc@53 { 529 compatible = "nxp,pcf2131"; 530 reg = <0x53>; 531 interrupt-parent = <&pcal6524>; 532 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 533 }; 534}; 535 536&lpuart1 { /* console */ 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_uart1>; 539 status = "okay"; 540}; 541 542&lpuart5 { 543 pinctrl-names = "default"; 544 pinctrl-0 = <&pinctrl_uart5>; 545 status = "okay"; 546 547 bluetooth { 548 compatible = "nxp,88w8987-bt"; 549 }; 550}; 551 552&micfil { 553 pinctrl-names = "default", "sleep"; 554 pinctrl-0 = <&pinctrl_pdm>; 555 pinctrl-1 = <&pinctrl_pdm_sleep>; 556 assigned-clocks = <&clk IMX93_CLK_PDM>; 557 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 558 assigned-clock-rates = <49152000>; 559 status = "okay"; 560}; 561 562&mu1 { 563 status = "okay"; 564}; 565 566&mu2 { 567 status = "okay"; 568}; 569 570&sai1 { 571 pinctrl-names = "default", "sleep"; 572 pinctrl-0 = <&pinctrl_sai1>; 573 pinctrl-1 = <&pinctrl_sai1_sleep>; 574 assigned-clocks = <&clk IMX93_CLK_SAI1>; 575 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 576 assigned-clock-rates = <12288000>; 577 fsl,sai-mclk-direction-output; 578 status = "okay"; 579}; 580 581&sai3 { 582 pinctrl-names = "default", "sleep"; 583 pinctrl-0 = <&pinctrl_sai3>; 584 pinctrl-1 = <&pinctrl_sai3_sleep>; 585 assigned-clocks = <&clk IMX93_CLK_SAI3>; 586 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 587 assigned-clock-rates = <12288000>; 588 fsl,sai-mclk-direction-output; 589 status = "okay"; 590}; 591 592&usbotg1 { 593 dr_mode = "otg"; 594 hnp-disable; 595 srp-disable; 596 adp-disable; 597 usb-role-switch; 598 disable-over-current; 599 samsung,picophy-pre-emp-curr-control = <3>; 600 samsung,picophy-dc-vol-level-adjust = <7>; 601 status = "okay"; 602 603 port { 604 usb1_drd_sw: endpoint { 605 remote-endpoint = <&typec1_dr_sw>; 606 }; 607 }; 608}; 609 610&usbotg2 { 611 dr_mode = "otg"; 612 hnp-disable; 613 srp-disable; 614 adp-disable; 615 usb-role-switch; 616 disable-over-current; 617 samsung,picophy-pre-emp-curr-control = <3>; 618 samsung,picophy-dc-vol-level-adjust = <7>; 619 status = "okay"; 620 621 port { 622 usb2_drd_sw: endpoint { 623 remote-endpoint = <&typec2_dr_sw>; 624 }; 625 }; 626}; 627 628&usdhc1 { 629 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 630 pinctrl-0 = <&pinctrl_usdhc1>; 631 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 632 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 633 bus-width = <8>; 634 non-removable; 635 status = "okay"; 636}; 637 638&usdhc2 { 639 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 640 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 641 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 642 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 643 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 644 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 645 vmmc-supply = <®_usdhc2_vmmc>; 646 bus-width = <4>; 647 status = "okay"; 648 no-mmc; 649}; 650 651&usdhc3 { 652 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 653 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; 654 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; 655 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; 656 pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; 657 mmc-pwrseq = <&usdhc3_pwrseq>; 658 vmmc-supply = <®_usdhc3_vmmc>; 659 bus-width = <4>; 660 keep-power-in-suspend; 661 non-removable; 662 wakeup-source; 663 status = "okay"; 664}; 665 666&wdog3 { 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pinctrl_wdog>; 669 fsl,ext-reset-output; 670 status = "okay"; 671}; 672 673&xcvr { 674 pinctrl-names = "default", "sleep"; 675 pinctrl-0 = <&pinctrl_spdif>; 676 pinctrl-1 = <&pinctrl_spdif_sleep>; 677 assigned-clocks = <&clk IMX93_CLK_SPDIF>, 678 <&clk IMX93_CLK_AUDIO_XCVR>; 679 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, 680 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 681 assigned-clock-rates = <12288000>, <200000000>; 682 status = "okay"; 683}; 684 685&iomuxc { 686 pinctrl_eqos: eqosgrp { 687 fsl,pins = < 688 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 689 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 690 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 691 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 692 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 693 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 694 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 695 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 696 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 697 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 698 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 699 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 700 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 701 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 702 >; 703 }; 704 705 pinctrl_eqos_sleep: eqossleepgrp { 706 fsl,pins = < 707 MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e 708 MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e 709 MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e 710 MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e 711 MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e 712 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e 713 MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e 714 MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e 715 MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e 716 MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e 717 MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e 718 MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e 719 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e 720 MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e 721 >; 722 }; 723 724 pinctrl_fec: fecgrp { 725 fsl,pins = < 726 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 727 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 728 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 729 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 730 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 731 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 732 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e 733 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 734 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 735 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 736 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 737 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 738 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 739 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 740 >; 741 }; 742 743 pinctrl_fec_sleep: fecsleepgrp { 744 fsl,pins = < 745 MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e 746 MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 747 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e 748 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e 749 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e 750 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e 751 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 752 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 753 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e 754 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e 755 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e 756 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e 757 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e 758 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 759 >; 760 }; 761 762 pinctrl_flexcan2: flexcan2grp { 763 fsl,pins = < 764 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 765 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 766 >; 767 }; 768 769 pinctrl_uart1: uart1grp { 770 fsl,pins = < 771 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 772 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 773 >; 774 }; 775 776 pinctrl_uart5: uart5grp { 777 fsl,pins = < 778 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 779 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 780 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 781 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 782 >; 783 }; 784 785 pinctrl_lpi2c1: lpi2c1grp { 786 fsl,pins = < 787 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 788 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 789 >; 790 }; 791 792 pinctrl_lpi2c2: lpi2c2grp { 793 fsl,pins = < 794 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 795 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 796 >; 797 }; 798 799 pinctrl_lpi2c3: lpi2c3grp { 800 fsl,pins = < 801 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 802 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 803 >; 804 }; 805 806 pinctrl_pcal6524: pcal6524grp { 807 fsl,pins = < 808 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 809 >; 810 }; 811 812 pinctrl_pdm: pdmgrp { 813 fsl,pins = < 814 MX93_PAD_PDM_CLK__PDM_CLK 0x31e 815 MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e 816 MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e 817 >; 818 }; 819 820 pinctrl_pdm_sleep: pdmsleepgrp { 821 fsl,pins = < 822 MX93_PAD_PDM_CLK__GPIO1_IO08 0x31e 823 MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x31e 824 MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e 825 >; 826 }; 827 828 pinctrl_sai1: sai1grp { 829 fsl,pins = < 830 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 831 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 832 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e 833 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e 834 >; 835 }; 836 837 pinctrl_sai1_sleep: sai1sleepgrp { 838 fsl,pins = < 839 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x51e 840 MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x51e 841 MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x51e 842 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e 843 >; 844 }; 845 846 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 847 pinctrl_usdhc1: usdhc1grp { 848 fsl,pins = < 849 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 850 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 851 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 852 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 853 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 854 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 855 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 856 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 857 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 858 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 859 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 860 >; 861 }; 862 863 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 864 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 865 fsl,pins = < 866 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 867 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 868 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 869 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 870 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 871 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 872 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 873 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 874 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 875 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 876 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 877 >; 878 }; 879 880 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 881 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 882 fsl,pins = < 883 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 884 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 885 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 886 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 887 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 888 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 889 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 890 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 891 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 892 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 893 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 894 >; 895 }; 896 897 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 898 fsl,pins = < 899 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 900 >; 901 }; 902 903 pinctrl_sai3: sai3grp { 904 fsl,pins = < 905 MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 906 MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 907 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e 908 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e 909 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e 910 >; 911 }; 912 913 pinctrl_sai3_sleep: sai3sleepgrp { 914 fsl,pins = < 915 MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e 916 MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e 917 MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e 918 MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e 919 MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e 920 >; 921 }; 922 923 pinctrl_spdif: spdifgrp { 924 fsl,pins = < 925 MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e 926 MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e 927 >; 928 }; 929 930 pinctrl_spdif_sleep: spdifsleepgrp { 931 fsl,pins = < 932 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e 933 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e 934 >; 935 }; 936 937 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 938 fsl,pins = < 939 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 940 >; 941 }; 942 943 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 944 fsl,pins = < 945 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e 946 >; 947 }; 948 949 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 950 pinctrl_usdhc2: usdhc2grp { 951 fsl,pins = < 952 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 953 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 954 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 955 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 956 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 957 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 958 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 959 >; 960 }; 961 962 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 963 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 964 fsl,pins = < 965 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 966 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 967 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 968 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 969 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 970 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 971 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 972 >; 973 }; 974 975 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 976 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 977 fsl,pins = < 978 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 979 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 980 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 981 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 982 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 983 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 984 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 985 >; 986 }; 987 988 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 989 fsl,pins = < 990 MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e 991 MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e 992 MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e 993 MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e 994 MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e 995 MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e 996 MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 997 >; 998 }; 999 1000 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 1001 pinctrl_usdhc3: usdhc3grp { 1002 fsl,pins = < 1003 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 1004 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 1005 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 1006 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 1007 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 1008 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 1009 >; 1010 }; 1011 1012 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 1013 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1014 fsl,pins = < 1015 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e 1016 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e 1017 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 1018 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 1019 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 1020 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 1021 >; 1022 }; 1023 1024 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 1025 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1026 fsl,pins = < 1027 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe 1028 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe 1029 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe 1030 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe 1031 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe 1032 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe 1033 >; 1034 }; 1035 1036 pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { 1037 fsl,pins = < 1038 MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e 1039 MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e 1040 MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e 1041 MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e 1042 MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e 1043 MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e 1044 >; 1045 }; 1046 1047 pinctrl_usdhc3_wlan: usdhc3wlangrp { 1048 fsl,pins = < 1049 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 1050 >; 1051 }; 1052 1053 pinctrl_wdog: wdoggrp { 1054 fsl,pins = < 1055 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 1056 >; 1057 }; 1058}; 1059