1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 11X11 EVK board"; 13 compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 14 15 chosen { 16 stdout-path = &lpuart1; 17 }; 18 19 reserved-memory { 20 #address-cells = <2>; 21 #size-cells = <2>; 22 ranges; 23 24 linux,cma { 25 compatible = "shared-dma-pool"; 26 reusable; 27 alloc-ranges = <0 0x80000000 0 0x40000000>; 28 size = <0 0x10000000>; 29 linux,cma-default; 30 }; 31 32 vdev0vring0: vdev0vring0@a4000000 { 33 reg = <0 0xa4000000 0 0x8000>; 34 no-map; 35 }; 36 37 vdev0vring1: vdev0vring1@a4008000 { 38 reg = <0 0xa4008000 0 0x8000>; 39 no-map; 40 }; 41 42 vdev1vring0: vdev1vring0@a4010000 { 43 reg = <0 0xa4010000 0 0x8000>; 44 no-map; 45 }; 46 47 vdev1vring1: vdev1vring1@a4018000 { 48 reg = <0 0xa4018000 0 0x8000>; 49 no-map; 50 }; 51 52 rsc_table: rsc-table@2021e000 { 53 reg = <0 0x2021e000 0 0x1000>; 54 no-map; 55 }; 56 57 vdevbuffer: vdevbuffer@a4020000 { 58 compatible = "shared-dma-pool"; 59 reg = <0 0xa4020000 0 0x100000>; 60 no-map; 61 }; 62 63 }; 64 65 reg_vref_1v8: regulator-adc-vref { 66 compatible = "regulator-fixed"; 67 regulator-name = "vref_1v8"; 68 regulator-min-microvolt = <1800000>; 69 regulator-max-microvolt = <1800000>; 70 }; 71 72 reg_usdhc2_vmmc: regulator-usdhc2 { 73 compatible = "regulator-fixed"; 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 76 regulator-name = "VSD_3V3"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 80 off-on-delay-us = <12000>; 81 enable-active-high; 82 }; 83}; 84 85&adc1 { 86 vref-supply = <®_vref_1v8>; 87 status = "okay"; 88}; 89 90&cm33 { 91 mbox-names = "tx", "rx", "rxdb"; 92 mboxes = <&mu1 0 1>, 93 <&mu1 1 1>, 94 <&mu1 3 1>; 95 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 96 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 97 status = "okay"; 98}; 99 100&eqos { 101 pinctrl-names = "default", "sleep"; 102 pinctrl-0 = <&pinctrl_eqos>; 103 pinctrl-1 = <&pinctrl_eqos_sleep>; 104 phy-mode = "rgmii-id"; 105 phy-handle = <ðphy1>; 106 status = "okay"; 107 108 mdio { 109 compatible = "snps,dwmac-mdio"; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 clock-frequency = <5000000>; 113 114 ethphy1: ethernet-phy@1 { 115 reg = <1>; 116 eee-broken-1000t; 117 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 118 reset-assert-us = <10000>; 119 reset-deassert-us = <80000>; 120 }; 121 }; 122}; 123 124&fec { 125 pinctrl-names = "default", "sleep"; 126 pinctrl-0 = <&pinctrl_fec>; 127 pinctrl-1 = <&pinctrl_fec_sleep>; 128 phy-mode = "rgmii-id"; 129 phy-handle = <ðphy2>; 130 fsl,magic-packet; 131 status = "okay"; 132 133 mdio { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 clock-frequency = <5000000>; 137 138 ethphy2: ethernet-phy@2 { 139 reg = <2>; 140 eee-broken-1000t; 141 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 142 reset-assert-us = <10000>; 143 reset-deassert-us = <80000>; 144 }; 145 }; 146}; 147 148&lpi2c2 { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 clock-frequency = <400000>; 152 pinctrl-names = "default", "sleep"; 153 pinctrl-0 = <&pinctrl_lpi2c2>; 154 pinctrl-1 = <&pinctrl_lpi2c2>; 155 status = "okay"; 156 157 pcal6524: gpio@22 { 158 compatible = "nxp,pcal6524"; 159 reg = <0x22>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_pcal6524>; 162 gpio-controller; 163 #gpio-cells = <2>; 164 interrupt-controller; 165 #interrupt-cells = <2>; 166 interrupt-parent = <&gpio3>; 167 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 168 }; 169 170 pmic@25 { 171 compatible = "nxp,pca9451a"; 172 reg = <0x25>; 173 interrupt-parent = <&pcal6524>; 174 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 175 176 regulators { 177 buck1: BUCK1 { 178 regulator-name = "BUCK1"; 179 regulator-min-microvolt = <610000>; 180 regulator-max-microvolt = <950000>; 181 regulator-boot-on; 182 regulator-always-on; 183 regulator-ramp-delay = <3125>; 184 }; 185 186 buck2: BUCK2 { 187 regulator-name = "BUCK2"; 188 regulator-min-microvolt = <600000>; 189 regulator-max-microvolt = <670000>; 190 regulator-boot-on; 191 regulator-always-on; 192 regulator-ramp-delay = <3125>; 193 }; 194 195 buck4: BUCK4{ 196 regulator-name = "BUCK4"; 197 regulator-min-microvolt = <1620000>; 198 regulator-max-microvolt = <3400000>; 199 regulator-boot-on; 200 regulator-always-on; 201 }; 202 203 buck5: BUCK5{ 204 regulator-name = "BUCK5"; 205 regulator-min-microvolt = <1620000>; 206 regulator-max-microvolt = <3400000>; 207 regulator-boot-on; 208 regulator-always-on; 209 }; 210 211 buck6: BUCK6 { 212 regulator-name = "BUCK6"; 213 regulator-min-microvolt = <1060000>; 214 regulator-max-microvolt = <1140000>; 215 regulator-boot-on; 216 regulator-always-on; 217 }; 218 219 ldo1: LDO1 { 220 regulator-name = "LDO1"; 221 regulator-min-microvolt = <1620000>; 222 regulator-max-microvolt = <1980000>; 223 regulator-boot-on; 224 regulator-always-on; 225 }; 226 227 ldo4: LDO4 { 228 regulator-name = "LDO4"; 229 regulator-min-microvolt = <800000>; 230 regulator-max-microvolt = <840000>; 231 regulator-boot-on; 232 regulator-always-on; 233 }; 234 235 ldo5: LDO5 { 236 regulator-name = "LDO5"; 237 regulator-min-microvolt = <1800000>; 238 regulator-max-microvolt = <3300000>; 239 regulator-boot-on; 240 regulator-always-on; 241 }; 242 }; 243 }; 244}; 245 246&lpi2c3 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 clock-frequency = <400000>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_lpi2c3>; 252 status = "okay"; 253 254 ptn5110: tcpc@50 { 255 compatible = "nxp,ptn5110", "tcpci"; 256 reg = <0x50>; 257 interrupt-parent = <&gpio3>; 258 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 259 260 typec1_con: connector { 261 compatible = "usb-c-connector"; 262 label = "USB-C"; 263 power-role = "dual"; 264 data-role = "dual"; 265 try-power-role = "sink"; 266 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 267 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 268 PDO_VAR(5000, 20000, 3000)>; 269 op-sink-microwatt = <15000000>; 270 self-powered; 271 272 ports { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 port@0 { 277 reg = <0>; 278 279 typec1_dr_sw: endpoint { 280 remote-endpoint = <&usb1_drd_sw>; 281 }; 282 }; 283 }; 284 }; 285 }; 286 287 ptn5110_2: tcpc@51 { 288 compatible = "nxp,ptn5110", "tcpci"; 289 reg = <0x51>; 290 interrupt-parent = <&gpio3>; 291 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 292 293 typec2_con: connector { 294 compatible = "usb-c-connector"; 295 label = "USB-C"; 296 power-role = "dual"; 297 data-role = "dual"; 298 try-power-role = "sink"; 299 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 300 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 301 PDO_VAR(5000, 20000, 3000)>; 302 op-sink-microwatt = <15000000>; 303 self-powered; 304 305 ports { 306 #address-cells = <1>; 307 #size-cells = <0>; 308 309 port@0 { 310 reg = <0>; 311 312 typec2_dr_sw: endpoint { 313 remote-endpoint = <&usb2_drd_sw>; 314 }; 315 }; 316 }; 317 }; 318 }; 319 320 pcf2131: rtc@53 { 321 compatible = "nxp,pcf2131"; 322 reg = <0x53>; 323 interrupt-parent = <&pcal6524>; 324 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 325 }; 326}; 327 328&lpuart1 { /* console */ 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_uart1>; 331 status = "okay"; 332}; 333 334&lpuart5 { 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_uart5>; 337 status = "okay"; 338}; 339 340&mu1 { 341 status = "okay"; 342}; 343 344&mu2 { 345 status = "okay"; 346}; 347 348&usbotg1 { 349 dr_mode = "otg"; 350 hnp-disable; 351 srp-disable; 352 adp-disable; 353 usb-role-switch; 354 disable-over-current; 355 samsung,picophy-pre-emp-curr-control = <3>; 356 samsung,picophy-dc-vol-level-adjust = <7>; 357 status = "okay"; 358 359 port { 360 usb1_drd_sw: endpoint { 361 remote-endpoint = <&typec1_dr_sw>; 362 }; 363 }; 364}; 365 366&usbotg2 { 367 dr_mode = "otg"; 368 hnp-disable; 369 srp-disable; 370 adp-disable; 371 usb-role-switch; 372 disable-over-current; 373 samsung,picophy-pre-emp-curr-control = <3>; 374 samsung,picophy-dc-vol-level-adjust = <7>; 375 status = "okay"; 376 377 port { 378 usb2_drd_sw: endpoint { 379 remote-endpoint = <&typec2_dr_sw>; 380 }; 381 }; 382}; 383 384&usdhc1 { 385 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 386 pinctrl-0 = <&pinctrl_usdhc1>; 387 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 388 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 389 bus-width = <8>; 390 non-removable; 391 status = "okay"; 392}; 393 394&usdhc2 { 395 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 396 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 397 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 398 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 399 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 400 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 401 vmmc-supply = <®_usdhc2_vmmc>; 402 bus-width = <4>; 403 status = "okay"; 404 no-mmc; 405}; 406 407&wdog3 { 408 status = "okay"; 409}; 410 411&iomuxc { 412 pinctrl_eqos: eqosgrp { 413 fsl,pins = < 414 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 415 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 416 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 417 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 418 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 419 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 420 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 421 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 422 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 423 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 424 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 425 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 426 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 427 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 428 >; 429 }; 430 431 pinctrl_eqos_sleep: eqossleepgrp { 432 fsl,pins = < 433 MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e 434 MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e 435 MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e 436 MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e 437 MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e 438 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e 439 MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e 440 MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e 441 MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e 442 MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e 443 MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e 444 MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e 445 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e 446 MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e 447 >; 448 }; 449 450 pinctrl_fec: fecgrp { 451 fsl,pins = < 452 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 453 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 454 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 455 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 456 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 457 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 458 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 459 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 460 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 461 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 462 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 463 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 464 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe 465 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 466 >; 467 }; 468 469 pinctrl_lpi2c3: lpi2c3grp { 470 fsl,pins = < 471 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 472 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 473 >; 474 }; 475 476 pinctrl_fec_sleep: fecsleepgrp { 477 fsl,pins = < 478 MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e 479 MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 480 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e 481 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e 482 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e 483 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e 484 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 485 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 486 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e 487 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e 488 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e 489 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e 490 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e 491 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 492 >; 493 }; 494 495 pinctrl_uart1: uart1grp { 496 fsl,pins = < 497 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 498 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 499 >; 500 }; 501 502 pinctrl_uart5: uart5grp { 503 fsl,pins = < 504 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 505 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 506 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 507 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 508 >; 509 }; 510 511 pinctrl_lpi2c2: lpi2c2grp { 512 fsl,pins = < 513 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 514 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 515 >; 516 }; 517 518 pinctrl_lpi2c3: lpi2c3grp { 519 fsl,pins = < 520 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 521 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 522 >; 523 }; 524 525 pinctrl_pcal6524: pcal6524grp { 526 fsl,pins = < 527 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 528 >; 529 }; 530 531 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 532 pinctrl_usdhc1: usdhc1grp { 533 fsl,pins = < 534 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 535 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 536 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 537 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 538 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 539 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 540 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 541 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 542 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 543 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 544 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 545 >; 546 }; 547 548 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 549 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 550 fsl,pins = < 551 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 552 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 553 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 554 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 555 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 556 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 557 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 558 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 559 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 560 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 561 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 562 >; 563 }; 564 565 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 566 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 567 fsl,pins = < 568 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 569 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 570 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 571 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 572 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 573 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 574 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 575 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 576 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 577 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 578 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 579 >; 580 }; 581 582 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 583 fsl,pins = < 584 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 585 >; 586 }; 587 588 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 589 fsl,pins = < 590 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 591 >; 592 }; 593 594 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 595 fsl,pins = < 596 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e 597 >; 598 }; 599 600 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 601 pinctrl_usdhc2: usdhc2grp { 602 fsl,pins = < 603 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 604 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 605 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 606 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 607 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 608 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 609 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 610 >; 611 }; 612 613 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 614 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 615 fsl,pins = < 616 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 617 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 618 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 619 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 620 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 621 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 622 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 623 >; 624 }; 625 626 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 627 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 628 fsl,pins = < 629 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 630 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 631 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 632 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 633 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 634 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 635 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 636 >; 637 }; 638 639 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 640 fsl,pins = < 641 MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e 642 MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e 643 MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e 644 MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e 645 MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e 646 MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e 647 MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 648 >; 649 }; 650 651}; 652