1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 11X11 EVK board"; 13 compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 14 15 chosen { 16 stdout-path = &lpuart1; 17 }; 18 19 reserved-memory { 20 #address-cells = <2>; 21 #size-cells = <2>; 22 ranges; 23 24 linux,cma { 25 compatible = "shared-dma-pool"; 26 reusable; 27 alloc-ranges = <0 0x80000000 0 0x40000000>; 28 size = <0 0x10000000>; 29 linux,cma-default; 30 }; 31 32 vdev0vring0: vdev0vring0@a4000000 { 33 reg = <0 0xa4000000 0 0x8000>; 34 no-map; 35 }; 36 37 vdev0vring1: vdev0vring1@a4008000 { 38 reg = <0 0xa4008000 0 0x8000>; 39 no-map; 40 }; 41 42 vdev1vring0: vdev1vring0@a4010000 { 43 reg = <0 0xa4010000 0 0x8000>; 44 no-map; 45 }; 46 47 vdev1vring1: vdev1vring1@a4018000 { 48 reg = <0 0xa4018000 0 0x8000>; 49 no-map; 50 }; 51 52 rsc_table: rsc-table@2021e000 { 53 reg = <0 0x2021e000 0 0x1000>; 54 no-map; 55 }; 56 57 vdevbuffer: vdevbuffer@a4020000 { 58 compatible = "shared-dma-pool"; 59 reg = <0 0xa4020000 0 0x100000>; 60 no-map; 61 }; 62 63 }; 64 65 reg_vref_1v8: regulator-adc-vref { 66 compatible = "regulator-fixed"; 67 regulator-name = "vref_1v8"; 68 regulator-min-microvolt = <1800000>; 69 regulator-max-microvolt = <1800000>; 70 }; 71 72 reg_usdhc2_vmmc: regulator-usdhc2 { 73 compatible = "regulator-fixed"; 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 76 regulator-name = "VSD_3V3"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 80 off-on-delay-us = <12000>; 81 enable-active-high; 82 }; 83}; 84 85&adc1 { 86 vref-supply = <®_vref_1v8>; 87 status = "okay"; 88}; 89 90&cm33 { 91 mbox-names = "tx", "rx", "rxdb"; 92 mboxes = <&mu1 0 1>, 93 <&mu1 1 1>, 94 <&mu1 3 1>; 95 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 96 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 97 status = "okay"; 98}; 99 100&mu1 { 101 status = "okay"; 102}; 103 104&mu2 { 105 status = "okay"; 106}; 107 108&lpi2c3 { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 clock-frequency = <400000>; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_lpi2c3>; 114 status = "okay"; 115 116 ptn5110: tcpc@50 { 117 compatible = "nxp,ptn5110", "tcpci"; 118 reg = <0x50>; 119 interrupt-parent = <&gpio3>; 120 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 121 122 typec1_con: connector { 123 compatible = "usb-c-connector"; 124 label = "USB-C"; 125 power-role = "dual"; 126 data-role = "dual"; 127 try-power-role = "sink"; 128 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 129 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 130 PDO_VAR(5000, 20000, 3000)>; 131 op-sink-microwatt = <15000000>; 132 self-powered; 133 134 ports { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 port@0 { 139 reg = <0>; 140 141 typec1_dr_sw: endpoint { 142 remote-endpoint = <&usb1_drd_sw>; 143 }; 144 }; 145 }; 146 }; 147 }; 148 149 ptn5110_2: tcpc@51 { 150 compatible = "nxp,ptn5110", "tcpci"; 151 reg = <0x51>; 152 interrupt-parent = <&gpio3>; 153 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 154 155 typec2_con: connector { 156 compatible = "usb-c-connector"; 157 label = "USB-C"; 158 power-role = "dual"; 159 data-role = "dual"; 160 try-power-role = "sink"; 161 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 162 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 163 PDO_VAR(5000, 20000, 3000)>; 164 op-sink-microwatt = <15000000>; 165 self-powered; 166 167 ports { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 port@0 { 172 reg = <0>; 173 174 typec2_dr_sw: endpoint { 175 remote-endpoint = <&usb2_drd_sw>; 176 }; 177 }; 178 }; 179 }; 180 }; 181}; 182 183&eqos { 184 pinctrl-names = "default", "sleep"; 185 pinctrl-0 = <&pinctrl_eqos>; 186 pinctrl-1 = <&pinctrl_eqos_sleep>; 187 phy-mode = "rgmii-id"; 188 phy-handle = <ðphy1>; 189 status = "okay"; 190 191 mdio { 192 compatible = "snps,dwmac-mdio"; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 clock-frequency = <5000000>; 196 197 ethphy1: ethernet-phy@1 { 198 reg = <1>; 199 eee-broken-1000t; 200 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 201 reset-assert-us = <10000>; 202 reset-deassert-us = <80000>; 203 }; 204 }; 205}; 206 207&fec { 208 pinctrl-names = "default", "sleep"; 209 pinctrl-0 = <&pinctrl_fec>; 210 pinctrl-1 = <&pinctrl_fec_sleep>; 211 phy-mode = "rgmii-id"; 212 phy-handle = <ðphy2>; 213 fsl,magic-packet; 214 status = "okay"; 215 216 mdio { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 clock-frequency = <5000000>; 220 221 ethphy2: ethernet-phy@2 { 222 reg = <2>; 223 eee-broken-1000t; 224 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 225 reset-assert-us = <10000>; 226 reset-deassert-us = <80000>; 227 }; 228 }; 229}; 230 231&lpuart1 { /* console */ 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_uart1>; 234 status = "okay"; 235}; 236 237&lpuart5 { 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_uart5>; 240 status = "okay"; 241}; 242 243&usbotg1 { 244 dr_mode = "otg"; 245 hnp-disable; 246 srp-disable; 247 adp-disable; 248 usb-role-switch; 249 disable-over-current; 250 samsung,picophy-pre-emp-curr-control = <3>; 251 samsung,picophy-dc-vol-level-adjust = <7>; 252 status = "okay"; 253 254 port { 255 usb1_drd_sw: endpoint { 256 remote-endpoint = <&typec1_dr_sw>; 257 }; 258 }; 259}; 260 261&usbotg2 { 262 dr_mode = "otg"; 263 hnp-disable; 264 srp-disable; 265 adp-disable; 266 usb-role-switch; 267 disable-over-current; 268 samsung,picophy-pre-emp-curr-control = <3>; 269 samsung,picophy-dc-vol-level-adjust = <7>; 270 status = "okay"; 271 272 port { 273 usb2_drd_sw: endpoint { 274 remote-endpoint = <&typec2_dr_sw>; 275 }; 276 }; 277}; 278 279&usdhc1 { 280 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 281 pinctrl-0 = <&pinctrl_usdhc1>; 282 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 283 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 284 bus-width = <8>; 285 non-removable; 286 status = "okay"; 287}; 288 289&usdhc2 { 290 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 291 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 292 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 293 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 294 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 295 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 296 vmmc-supply = <®_usdhc2_vmmc>; 297 bus-width = <4>; 298 status = "okay"; 299 no-sdio; 300 no-mmc; 301}; 302 303&wdog3 { 304 status = "okay"; 305}; 306 307&lpi2c2 { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clock-frequency = <400000>; 311 pinctrl-names = "default", "sleep"; 312 pinctrl-0 = <&pinctrl_lpi2c2>; 313 pinctrl-1 = <&pinctrl_lpi2c2>; 314 status = "okay"; 315 316 pcal6524: gpio@22 { 317 compatible = "nxp,pcal6524"; 318 reg = <0x22>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pinctrl_pcal6524>; 321 gpio-controller; 322 #gpio-cells = <2>; 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 interrupt-parent = <&gpio3>; 326 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 327 }; 328 329 pmic@25 { 330 compatible = "nxp,pca9451a"; 331 reg = <0x25>; 332 interrupt-parent = <&pcal6524>; 333 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 334 335 regulators { 336 buck1: BUCK1 { 337 regulator-name = "BUCK1"; 338 regulator-min-microvolt = <610000>; 339 regulator-max-microvolt = <950000>; 340 regulator-boot-on; 341 regulator-always-on; 342 regulator-ramp-delay = <3125>; 343 }; 344 345 buck2: BUCK2 { 346 regulator-name = "BUCK2"; 347 regulator-min-microvolt = <600000>; 348 regulator-max-microvolt = <670000>; 349 regulator-boot-on; 350 regulator-always-on; 351 regulator-ramp-delay = <3125>; 352 }; 353 354 buck4: BUCK4{ 355 regulator-name = "BUCK4"; 356 regulator-min-microvolt = <1620000>; 357 regulator-max-microvolt = <3400000>; 358 regulator-boot-on; 359 regulator-always-on; 360 }; 361 362 buck5: BUCK5{ 363 regulator-name = "BUCK5"; 364 regulator-min-microvolt = <1620000>; 365 regulator-max-microvolt = <3400000>; 366 regulator-boot-on; 367 regulator-always-on; 368 }; 369 370 buck6: BUCK6 { 371 regulator-name = "BUCK6"; 372 regulator-min-microvolt = <1060000>; 373 regulator-max-microvolt = <1140000>; 374 regulator-boot-on; 375 regulator-always-on; 376 }; 377 378 ldo1: LDO1 { 379 regulator-name = "LDO1"; 380 regulator-min-microvolt = <1620000>; 381 regulator-max-microvolt = <1980000>; 382 regulator-boot-on; 383 regulator-always-on; 384 }; 385 386 ldo4: LDO4 { 387 regulator-name = "LDO4"; 388 regulator-min-microvolt = <800000>; 389 regulator-max-microvolt = <840000>; 390 regulator-boot-on; 391 regulator-always-on; 392 }; 393 394 ldo5: LDO5 { 395 regulator-name = "LDO5"; 396 regulator-min-microvolt = <1800000>; 397 regulator-max-microvolt = <3300000>; 398 regulator-boot-on; 399 regulator-always-on; 400 }; 401 }; 402 }; 403}; 404 405&lpi2c3 { 406 clock-frequency = <400000>; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_lpi2c3>; 409 status = "okay"; 410 411 pcf2131: rtc@53 { 412 compatible = "nxp,pcf2131"; 413 reg = <0x53>; 414 interrupt-parent = <&pcal6524>; 415 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 416 }; 417}; 418 419&iomuxc { 420 pinctrl_eqos: eqosgrp { 421 fsl,pins = < 422 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 423 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 424 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 425 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 426 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 427 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 428 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 429 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 430 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 431 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 432 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 433 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 434 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 435 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 436 >; 437 }; 438 439 pinctrl_eqos_sleep: eqossleepgrp { 440 fsl,pins = < 441 MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e 442 MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e 443 MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e 444 MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e 445 MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e 446 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e 447 MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e 448 MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e 449 MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e 450 MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e 451 MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e 452 MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e 453 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e 454 MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e 455 >; 456 }; 457 458 pinctrl_fec: fecgrp { 459 fsl,pins = < 460 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 461 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 462 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 463 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 464 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 465 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 466 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 467 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 468 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 469 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 470 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 471 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 472 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe 473 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 474 >; 475 }; 476 477 pinctrl_lpi2c3: lpi2c3grp { 478 fsl,pins = < 479 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 480 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 481 >; 482 }; 483 484 pinctrl_fec_sleep: fecsleepgrp { 485 fsl,pins = < 486 MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e 487 MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 488 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e 489 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e 490 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e 491 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e 492 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 493 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 494 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e 495 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e 496 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e 497 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e 498 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e 499 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 500 >; 501 }; 502 503 pinctrl_uart1: uart1grp { 504 fsl,pins = < 505 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 506 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 507 >; 508 }; 509 510 pinctrl_uart5: uart5grp { 511 fsl,pins = < 512 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 513 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 514 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 515 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 516 >; 517 }; 518 519 pinctrl_lpi2c2: lpi2c2grp { 520 fsl,pins = < 521 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 522 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 523 >; 524 }; 525 526 pinctrl_lpi2c3: lpi2c3grp { 527 fsl,pins = < 528 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 529 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 530 >; 531 }; 532 533 pinctrl_pcal6524: pcal6524grp { 534 fsl,pins = < 535 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 536 >; 537 }; 538 539 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 540 pinctrl_usdhc1: usdhc1grp { 541 fsl,pins = < 542 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 543 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 544 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 545 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 546 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 547 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 548 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 549 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 550 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 551 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 552 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 553 >; 554 }; 555 556 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 557 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 558 fsl,pins = < 559 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 560 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 561 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 562 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 563 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 564 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 565 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 566 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 567 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 568 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 569 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 570 >; 571 }; 572 573 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 574 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 575 fsl,pins = < 576 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 577 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 578 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 579 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 580 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 581 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 582 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 583 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 584 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 585 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 586 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 587 >; 588 }; 589 590 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 591 fsl,pins = < 592 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 593 >; 594 }; 595 596 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 597 fsl,pins = < 598 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 599 >; 600 }; 601 602 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 603 fsl,pins = < 604 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e 605 >; 606 }; 607 608 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 609 pinctrl_usdhc2: usdhc2grp { 610 fsl,pins = < 611 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 612 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 613 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 614 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 615 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 616 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 617 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 618 >; 619 }; 620 621 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 622 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 623 fsl,pins = < 624 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 625 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 626 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 627 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 628 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 629 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 630 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 631 >; 632 }; 633 634 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 635 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 636 fsl,pins = < 637 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 638 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 639 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 640 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 641 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 642 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 643 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 644 >; 645 }; 646 647 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 648 fsl,pins = < 649 MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e 650 MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e 651 MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e 652 MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e 653 MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e 654 MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e 655 MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 656 >; 657 }; 658 659}; 660