1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx93.dtsi" 9 10/ { 11 model = "NXP i.MX93 11X11 EVK board"; 12 compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 13 14 chosen { 15 stdout-path = &lpuart1; 16 }; 17 18 reg_usdhc2_vmmc: regulator-usdhc2 { 19 compatible = "regulator-fixed"; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 22 regulator-name = "VSD_3V3"; 23 regulator-min-microvolt = <3300000>; 24 regulator-max-microvolt = <3300000>; 25 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 26 enable-active-high; 27 }; 28}; 29 30&mu1 { 31 status = "okay"; 32}; 33 34&mu2 { 35 status = "okay"; 36}; 37 38&eqos { 39 pinctrl-names = "default"; 40 pinctrl-0 = <&pinctrl_eqos>; 41 phy-mode = "rgmii-id"; 42 phy-handle = <ðphy1>; 43 status = "okay"; 44 45 mdio { 46 compatible = "snps,dwmac-mdio"; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 clock-frequency = <5000000>; 50 51 ethphy1: ethernet-phy@1 { 52 reg = <1>; 53 eee-broken-1000t; 54 }; 55 }; 56}; 57 58&fec { 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_fec>; 61 phy-mode = "rgmii-id"; 62 phy-handle = <ðphy2>; 63 fsl,magic-packet; 64 status = "okay"; 65 66 mdio { 67 #address-cells = <1>; 68 #size-cells = <0>; 69 clock-frequency = <5000000>; 70 71 ethphy2: ethernet-phy@2 { 72 reg = <2>; 73 eee-broken-1000t; 74 }; 75 }; 76}; 77 78&lpuart1 { /* console */ 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_uart1>; 81 status = "okay"; 82}; 83 84&usdhc1 { 85 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 86 pinctrl-0 = <&pinctrl_usdhc1>; 87 pinctrl-1 = <&pinctrl_usdhc1>; 88 pinctrl-2 = <&pinctrl_usdhc1>; 89 bus-width = <8>; 90 non-removable; 91 status = "okay"; 92}; 93 94&usdhc2 { 95 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 96 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 97 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 98 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 99 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 100 vmmc-supply = <®_usdhc2_vmmc>; 101 bus-width = <4>; 102 status = "okay"; 103 no-sdio; 104 no-mmc; 105}; 106 107&iomuxc { 108 pinctrl_eqos: eqosgrp { 109 fsl,pins = < 110 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 111 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 112 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 113 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 114 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 115 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 116 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 117 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 118 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 119 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 120 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 121 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 122 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 123 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 124 >; 125 }; 126 127 pinctrl_fec: fecgrp { 128 fsl,pins = < 129 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 130 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 131 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 132 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 133 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 134 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 135 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 136 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 137 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 138 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 139 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 140 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 141 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe 142 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 143 >; 144 }; 145 146 pinctrl_uart1: uart1grp { 147 fsl,pins = < 148 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 149 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 150 >; 151 }; 152 153 pinctrl_usdhc1: usdhc1grp { 154 fsl,pins = < 155 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 156 MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe 157 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 158 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 159 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 160 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 161 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 162 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 163 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 164 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 165 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 166 >; 167 }; 168 169 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 170 fsl,pins = < 171 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 172 >; 173 }; 174 175 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 176 fsl,pins = < 177 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 178 >; 179 }; 180 181 pinctrl_usdhc2: usdhc2grp { 182 fsl,pins = < 183 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 184 MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe 185 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 186 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 187 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 188 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 189 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 190 >; 191 }; 192}; 193