1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2019 Toradex 4 */ 5 6/ { 7 chosen { 8 stdout-path = &lpuart3; 9 }; 10 11 colibri_gpio_keys: gpio-keys { 12 compatible = "gpio-keys"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_gpiokeys>; 15 status = "disabled"; 16 17 key-wakeup { 18 debounce-interval = <10>; 19 gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; 20 label = "Wake-Up"; 21 linux,code = <KEY_WAKEUP>; 22 wakeup-source; 23 }; 24 }; 25 26 extcon_usbc_det: usbc-det { 27 compatible = "linux,extcon-usb-gpio"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_usbc_det>; 30 id-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; 31 status = "disabled"; 32 }; 33 34 reg_module_3v3: regulator-module-3v3 { 35 compatible = "regulator-fixed"; 36 regulator-name = "+V3.3"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 }; 40 41 reg_module_3v3_avdd: regulator-module-3v3-avdd { 42 compatible = "regulator-fixed"; 43 regulator-max-microvolt = <3300000>; 44 regulator-min-microvolt = <3300000>; 45 regulator-name = "+V3.3_AVDD_AUDIO"; 46 }; 47 48 reg_module_vref_1v8: regulator-module-vref-1v8 { 49 compatible = "regulator-fixed"; 50 regulator-max-microvolt = <1800000>; 51 regulator-min-microvolt = <1800000>; 52 regulator-name = "vref-1v8"; 53 }; 54 55 reg_module_wifi: regulator-module-wifi { 56 compatible = "regulator-fixed"; 57 gpio = <&gpio_expander_43 6 GPIO_ACTIVE_HIGH>; 58 enable-active-high; 59 regulator-always-on; 60 regulator-name = "Wi-Fi_PDn"; 61 startup-delay-us = <2000>; 62 }; 63 64 reg_usbh_vbus: regulator-usbh-vbus { 65 compatible = "regulator-fixed"; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_usbh1_reg>; 68 gpio = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>; 69 regulator-always-on; 70 regulator-max-microvolt = <5000000>; 71 regulator-min-microvolt = <5000000>; 72 regulator-name = "usbh_vbus"; 73 }; 74 75 sound-card { 76 compatible = "simple-audio-card"; 77 simple-audio-card,bitclock-master = <&dailink_master>; 78 simple-audio-card,format = "i2s"; 79 simple-audio-card,frame-master = <&dailink_master>; 80 simple-audio-card,name = "colibri-imx8x"; 81 82 dailink_master: simple-audio-card,codec { 83 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 84 sound-dai = <&sgtl5000_a>; 85 }; 86 87 simple-audio-card,cpu { 88 sound-dai = <&sai0>; 89 }; 90 }; 91}; 92 93/* Colibri Analogue Inputs */ 94&adc0 { 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_adc0>; 97 vref-supply = <®_module_vref_1v8>; 98}; 99 100/* Colibri PWM_A */ 101&adma_pwm { 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_pwm_a>; 104}; 105 106&cpu_alert0 { 107 hysteresis = <2000>; 108 temperature = <90000>; 109 type = "passive"; 110}; 111 112&cpu_crit0 { 113 hysteresis = <2000>; 114 temperature = <105000>; 115 type = "critical"; 116}; 117 118&enet0_lpcg { 119 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 120 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 121 <&conn_axi_clk>, 122 <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, 123 <&conn_ipg_clk>, 124 <&conn_ipg_clk>; 125 clock-output-names = "enet0_lpcg_timer_clk", 126 "enet0_lpcg_txc_sampling_clk", 127 "enet0_lpcg_ahb_clk", 128 "enet0_lpcg_ref_50mhz_clk", 129 "enet0_lpcg_ipg_clk", 130 "enet0_lpcg_ipg_s_clk"; 131}; 132 133/* On-module I2C */ 134&i2c0 { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 clock-frequency = <100000>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; 140 status = "okay"; 141 142 /* USB HUB USB3803 */ 143 usb-hub@8 { 144 compatible = "smsc,usb3803"; 145 reg = <0x8>; 146 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 147 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 148 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 149 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 150 assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_usb3503a>; 153 bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>; 154 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 155 clock-names = "refclk"; 156 disabled-ports = <2>; 157 initial-mode = <1>; 158 intn-gpios = <&lsio_gpio3 4 GPIO_ACTIVE_LOW>; 159 reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>; 160 }; 161 162 sgtl5000_a: audio-codec@a { 163 compatible = "fsl,sgtl5000"; 164 reg = <0xa>; 165 #sound-dai-cells = <0>; 166 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 167 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 168 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 169 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 170 assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; 171 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 172 VDDA-supply = <®_module_3v3_avdd>; 173 VDDD-supply = <®_module_vref_1v8>; 174 VDDIO-supply = <®_module_3v3>; 175 }; 176 177 /* Touch controller */ 178 ad7879_ts: touchscreen@2c { 179 compatible = "adi,ad7879-1"; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_ad7879_int>; 182 reg = <0x2c>; 183 interrupt-parent = <&lsio_gpio3>; 184 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 185 touchscreen-max-pressure = <4096>; 186 adi,resistance-plate-x = <120>; 187 adi,first-conversion-delay = /bits/ 8 <3>; 188 adi,acquisition-time = /bits/ 8 <1>; 189 adi,median-filter-size = /bits/ 8 <2>; 190 adi,averaging = /bits/ 8 <1>; 191 adi,conversion-interval = /bits/ 8 <255>; 192 status = "disabled"; 193 }; 194 195 gpio_expander_43: gpio@43 { 196 compatible = "fcs,fxl6408"; 197 reg = <0x43>; 198 gpio-controller; 199 #gpio-cells = <2>; 200 gpio-line-names = "Wi-Fi_W_DISABLE", 201 "Wi-Fi_WKUP_WLAN", 202 "PWR_EN_+V3.3_WiFi_N", 203 "PCIe_REF_CLK_EN", 204 "USB_RESET_N", 205 "USB_BYPASS_N", 206 "Wi-Fi_PDn", 207 "Wi-Fi_WKUP_BT"; 208 }; 209}; 210 211/* TODO i2c lvds0 accessible on FFC (X2) */ 212 213/* TODO i2c lvds1 accessible on FFC (X3) */ 214 215/* Colibri I2C */ 216&i2c1 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 clock-frequency = <100000>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_i2c1>; 222}; 223 224&jpegdec { 225 status = "okay"; 226}; 227 228&jpegenc { 229 status = "okay"; 230}; 231 232/* TODO Parallel RRB */ 233 234/* Colibri UART_B */ 235&lpuart0 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_lpuart0>; 238}; 239 240/* Colibri UART_C */ 241&lpuart2 { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_lpuart2>; 244}; 245 246/* Colibri UART_A */ 247&lpuart3 { 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; 250}; 251 252/* Colibri FastEthernet */ 253&fec1 { 254 pinctrl-names = "default", "sleep"; 255 pinctrl-0 = <&pinctrl_fec1>; 256 pinctrl-1 = <&pinctrl_fec1_sleep>; 257 phy-mode = "rmii"; 258 phy-handle = <ðphy0>; 259 fsl,magic-packet; 260 261 mdio { 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 ethphy0: ethernet-phy@2 { 266 compatible = "ethernet-phy-ieee802.3-c22"; 267 max-speed = <100>; 268 reg = <2>; 269 }; 270 }; 271}; 272 273&hsio_phy { 274 fsl,hsio-cfg = "pciea-x2-pcieb"; 275 fsl,refclk-pad-mode = "input"; 276 status = "okay"; 277}; 278 279&hsio_refb_clk { 280 enable-gpios = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>; 281}; 282 283/* Colibri SPI */ 284&lpspi2 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_lpspi2>; 287 cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; 288}; 289 290&lsio_gpio0 { 291 gpio-line-names = "", 292 "SODIMM_70", 293 "SODIMM_60", 294 "SODIMM_58", 295 "SODIMM_78", 296 "SODIMM_72", 297 "SODIMM_80", 298 "SODIMM_46", 299 "SODIMM_62", 300 "SODIMM_48", 301 "SODIMM_74", 302 "SODIMM_50", 303 "SODIMM_52", 304 "SODIMM_54", 305 "SODIMM_66", 306 "SODIMM_64", 307 "SODIMM_68", 308 "", 309 "", 310 "SODIMM_82", 311 "SODIMM_56", 312 "SODIMM_28", 313 "SODIMM_30", 314 "", 315 "SODIMM_61", 316 "SODIMM_103", 317 "SODIMM_79", 318 "SODIMM_97", 319 "", 320 "SODIMM_25", 321 "SODIMM_27", 322 "SODIMM_100"; 323}; 324 325&lsio_gpio1 { 326 gpio-line-names = "SODIMM_86", 327 "SODIMM_92", 328 "SODIMM_90", 329 "SODIMM_88", 330 "", 331 "", 332 "", 333 "SODIMM_59", 334 "", 335 "SODIMM_6", 336 "SODIMM_8", 337 "", 338 "", 339 "SODIMM_2", 340 "SODIMM_4", 341 "SODIMM_34", 342 "SODIMM_32", 343 "SODIMM_63", 344 "SODIMM_55", 345 "SODIMM_33", 346 "SODIMM_35", 347 "SODIMM_36", 348 "SODIMM_38", 349 "SODIMM_21", 350 "SODIMM_19", 351 "SODIMM_140", 352 "SODIMM_142", 353 "SODIMM_196", 354 "SODIMM_194", 355 "SODIMM_186", 356 "SODIMM_188", 357 "SODIMM_138"; 358}; 359 360&lsio_gpio2 { 361 gpio-line-names = "SODIMM_23", 362 "", 363 "", 364 "SODIMM_144"; 365}; 366 367&lsio_gpio3 { 368 gpio-line-names = "SODIMM_96", 369 "SODIMM_75", 370 "SODIMM_37", 371 "SODIMM_29", 372 "", 373 "", 374 "", 375 "", 376 "", 377 "SODIMM_43", 378 "SODIMM_45", 379 "SODIMM_69", 380 "SODIMM_71", 381 "SODIMM_73", 382 "SODIMM_77", 383 "SODIMM_89", 384 "SODIMM_93", 385 "SODIMM_95", 386 "SODIMM_99", 387 "SODIMM_105", 388 "SODIMM_107", 389 "SODIMM_98", 390 "SODIMM_102", 391 "SODIMM_104", 392 "SODIMM_106"; 393}; 394 395&lsio_gpio4 { 396 gpio-line-names = "", 397 "", 398 "", 399 "SODIMM_129", 400 "SODIMM_133", 401 "SODIMM_127", 402 "SODIMM_131", 403 "", 404 "", 405 "", 406 "", 407 "", 408 "", 409 "", 410 "", 411 "", 412 "", 413 "", 414 "", 415 "SODIMM_44", 416 "", 417 "SODIMM_76", 418 "SODIMM_31", 419 "SODIMM_47", 420 "SODIMM_190", 421 "SODIMM_192", 422 "SODIMM_49", 423 "SODIMM_51", 424 "SODIMM_53"; 425}; 426 427&lsio_gpio5 { 428 gpio-line-names = "", 429 "SODIMM_57", 430 "SODIMM_65", 431 "SODIMM_85", 432 "", 433 "", 434 "", 435 "", 436 "SODIMM_135", 437 "SODIMM_137", 438 "UNUSABLE_SODIMM_180", 439 "UNUSABLE_SODIMM_184"; 440}; 441 442/* Colibri PWM_B */ 443&lsio_pwm0 { 444 #pwm-cells = <3>; 445 pinctrl-0 = <&pinctrl_pwm_b>; 446 pinctrl-names = "default"; 447}; 448 449/* Colibri PWM_C */ 450&lsio_pwm1 { 451 #pwm-cells = <3>; 452 pinctrl-0 = <&pinctrl_pwm_c>; 453 pinctrl-names = "default"; 454}; 455 456/* Colibri PWM_D */ 457&lsio_pwm2 { 458 #pwm-cells = <3>; 459 pinctrl-0 = <&pinctrl_pwm_d>; 460 pinctrl-names = "default"; 461}; 462 463/* VPU Mailboxes */ 464&mu_m0 { 465 status="okay"; 466}; 467 468&mu1_m0 { 469 status="okay"; 470}; 471 472/* TODO MIPI CSI */ 473 474/* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */ 475 476/* On-module PCIe for Wi-Fi */ 477&pcieb { 478 pinctrl-names = "default"; 479 pinctrl-0 = <&pinctrl_pcieb>; 480 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 481 phy-names = "pcie-phy"; 482 reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; 483 status = "okay"; 484}; 485 486/* On-module I2S */ 487&sai0 { 488 #sound-dai-cells = <0>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pinctrl_sai0>; 491 status = "okay"; 492}; 493 494&thermal_zones { 495 pmic-thermal { 496 polling-delay-passive = <250>; 497 polling-delay = <2000>; 498 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 499 500 trips { 501 pmic_alert0: trip0 { 502 temperature = <110000>; 503 hysteresis = <2000>; 504 type = "passive"; 505 }; 506 507 pmic_crit0: trip1 { 508 temperature = <125000>; 509 hysteresis = <2000>; 510 type = "critical"; 511 }; 512 }; 513 514 cooling-maps { 515 pmic_cooling_map0: map0 { 516 trip = <&pmic_alert0>; 517 cooling-device = <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 518 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 519 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 520 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 521 }; 522 }; 523 }; 524}; 525 526&usbotg1 { 527 adp-disable; 528 disable-over-current; 529 extcon = <&extcon_usbc_det &extcon_usbc_det>; 530 hnp-disable; 531 power-active-high; 532 srp-disable; 533 vbus-supply = <®_usbh_vbus>; 534}; 535 536&usbotg3_cdns3 { 537 dr_mode = "host"; 538}; 539 540/* On-module eMMC */ 541&usdhc1 { 542 bus-width = <8>; 543 non-removable; 544 no-sd; 545 no-sdio; 546 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 547 pinctrl-0 = <&pinctrl_usdhc1>; 548 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 549 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 550 status = "okay"; 551}; 552 553/* Colibri SD/MMC Card */ 554&usdhc2 { 555 bus-width = <4>; 556 cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; 557 vmmc-supply = <®_module_3v3>; 558 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 559 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 560 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 561 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 562 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 563 disable-wp; 564 no-1-8-v; 565}; 566 567&vpu { 568 compatible = "nxp,imx8qxp-vpu"; 569 status = "okay"; 570}; 571 572/* VPU Decoder */ 573&vpu_core0 { 574 reg = <0x2d040000 0x10000>; 575 memory-region = <&decoder_boot>, <&decoder_rpc>; 576 status = "okay"; 577}; 578 579/* VPU Encoder */ 580&vpu_core1 { 581 reg = <0x2d050000 0x10000>; 582 memory-region = <&encoder_boot>, <&encoder_rpc>; 583 status = "okay"; 584}; 585 586&iomuxc { 587 /* On-module touch pen-down interrupt */ 588 pinctrl_ad7879_int: ad7879intgrp { 589 fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21>; 590 }; 591 592 /* Colibri Analogue Inputs */ 593 pinctrl_adc0: adc0grp { 594 fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60>, /* SODIMM 8 */ 595 <IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60>, /* SODIMM 6 */ 596 <IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60>, /* SODIMM 4 */ 597 <IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60>; /* SODIMM 2 */ 598 }; 599 600 /* Atmel MXT touchsceen + Capacitive Touch Adapter */ 601 /* NOTE: This pingroup conflicts with pingroups 602 * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them 603 * simultaneously. 604 */ 605 pinctrl_atmel_adap: atmeladaptergrp { 606 fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21>, /* SODIMM 30 */ 607 <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021>; /* SODIMM 28 */ 608 }; 609 610 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ 611 pinctrl_atmel_conn: atmelconnectorgrp { 612 fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021>, /* SODIMM 107 */ 613 <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21>; /* SODIMM 106 */ 614 }; 615 616 pinctrl_can_int: canintgrp { 617 fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40>; /* SODIMM 73 */ 618 }; 619 620 pinctrl_csi_ctl: csictlgrp { 621 fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20>, /* SODIMM 77 */ 622 <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20>; /* SODIMM 89 */ 623 }; 624 625 pinctrl_csi_mclk: csimclkgrp { 626 fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041>; /* SODIMM 75 / X3-12 */ 627 }; 628 629 pinctrl_ext_io0: extio0grp { 630 fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040>; /* SODIMM 135 */ 631 }; 632 633 /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ 634 pinctrl_fec1: fec1grp { 635 fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020>, 636 <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>, 637 <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61>, 638 <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061>, 639 <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61>, 640 <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61>, 641 <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61>, 642 <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61>, 643 <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61>, 644 <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61>; 645 }; 646 647 pinctrl_fec1_sleep: fec1slpgrp { 648 fsl,pins = <IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041>, 649 <IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041>, 650 <IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41>, 651 <IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41>, 652 <IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41>, 653 <IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41>, 654 <IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41>, 655 <IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41>, 656 <IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41>, 657 <IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41>; 658 }; 659 660 /* Colibri optional CAN on UART_B RTS/CTS */ 661 pinctrl_flexcan1: flexcan0grp { 662 fsl,pins = <IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21>, /* SODIMM 32 */ 663 <IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21>; /* SODIMM 34 */ 664 }; 665 666 /* Colibri optional CAN on PS2 */ 667 pinctrl_flexcan2: flexcan1grp { 668 fsl,pins = <IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21>, /* SODIMM 55 */ 669 <IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21>; /* SODIMM 63 */ 670 }; 671 672 /* Colibri optional CAN on UART_A TXD/RXD */ 673 pinctrl_flexcan3: flexcan2grp { 674 fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21>, /* SODIMM 35 */ 675 <IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21>; /* SODIMM 33 */ 676 }; 677 678 /* Colibri LCD Back-Light GPIO */ 679 pinctrl_gpio_bl_on: gpioblongrp { 680 fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60>; /* SODIMM 71 */ 681 }; 682 683 /* HDMI Hot Plug Detect on FFC (X2) */ 684 pinctrl_gpio_hpd: gpiohpdgrp { 685 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20>; /* SODIMM 138 */ 686 }; 687 688 pinctrl_gpiokeys: gpiokeysgrp { 689 fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */ 690 }; 691 692 pinctrl_hog0: hog0grp { 693 fsl,pins = <IMX8QXP_CSI_D07_CI_PI_D09 0x61>, /* SODIMM 65 */ 694 <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20>, /* SODIMM 69 */ 695 <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */ 696 <IMX8QXP_CSI_D02_CI_PI_D04 0x61>, /* SODIMM 79 */ 697 <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */ 698 <IMX8QXP_CSI_D06_CI_PI_D08 0x61>, /* SODIMM 85 */ 699 <IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */ 700 <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */ 701 <IMX8QXP_CSI_D03_CI_PI_D05 0x61>, /* SODIMM 97 */ 702 <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>, /* SODIMM 99 */ 703 <IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */ 704 <IMX8QXP_CSI_D00_CI_PI_D02 0x61>, /* SODIMM 101 */ 705 <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */ 706 <IMX8QXP_CSI_D01_CI_PI_D03 0x61>, /* SODIMM 103 */ 707 <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20>, /* SODIMM 105 */ 708 <IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20>, /* SODIMM 127 */ 709 <IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20>, /* SODIMM 131 */ 710 <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20>, /* SODIMM 133 */ 711 <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20>, /* SODIMM 96 */ 712 <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */ 713 <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>, /* SODIMM 100 */ 714 <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20>, /* SODIMM 102 */ 715 <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20>; /* SODIMM 104 */ 716 }; 717 718 pinctrl_hog1: hog1grp { 719 fsl,pins = <IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20>; /* SODIMM 93 */ 720 }; 721 722 pinctrl_hog2: hog2grp { 723 fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>; /* SODIMM 75 */ 724 }; 725 726 /* 727 * This pin is used in the SCFW as a UART. Using it from 728 * Linux would require rewriting the SCFW board file. 729 */ 730 pinctrl_hog_scfw: hogscfwgrp { 731 fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20>; /* SODIMM 144 */ 732 }; 733 734 /* On Module I2C */ 735 pinctrl_i2c0: i2c0grp { 736 fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021>, 737 <IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021>; 738 }; 739 740 /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ 741 pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp { 742 fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020>, /* SODIMM 140 */ 743 <IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020>; /* SODIMM 142 */ 744 }; 745 746 /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ 747 pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp { 748 fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020>, /* SODIMM 186 */ 749 <IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020>; /* SODIMM 188 */ 750 }; 751 752 /* Colibri I2C */ 753 pinctrl_i2c1: i2c1grp { 754 fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021>, /* SODIMM 196 */ 755 <IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021>; /* SODIMM 194 */ 756 }; 757 758 /* Colibri Parallel RGB LCD Interface */ 759 pinctrl_lcdif: lcdifgrp { 760 fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60>, /* SODIMM 56 */ 761 <IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60>, /* SODIMM 68 */ 762 <IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60>, /* SODIMM 82 */ 763 <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x40>, /* SODIMM 44 */ 764 <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x40>, /* SODIMM 44 */ 765 <IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60>, /* SODIMM 76 */ 766 <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60>, /* SODIMM 76 */ 767 <IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60>, /* SODIMM 70 */ 768 <IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60>, /* SODIMM 60 */ 769 <IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60>, /* SODIMM 58 */ 770 <IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60>, /* SODIMM 78 */ 771 <IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60>, /* SODIMM 72 */ 772 <IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60>, /* SODIMM 80 */ 773 <IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60>, /* SODIMM 46 */ 774 <IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60>, /* SODIMM 62 */ 775 <IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60>, /* SODIMM 48 */ 776 <IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60>, /* SODIMM 74 */ 777 <IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60>, /* SODIMM 50 */ 778 <IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60>, /* SODIMM 52 */ 779 <IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60>, /* SODIMM 54 */ 780 <IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60>, /* SODIMM 66 */ 781 <IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60>, /* SODIMM 64 */ 782 <IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60>, /* SODIMM 57 */ 783 <IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60>, /* SODIMM 57 */ 784 <IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60>; /* SODIMM 61 */ 785 }; 786 787 /* Colibri SPI */ 788 pinctrl_lpspi2: lpspi2grp { 789 fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21>, /* SODIMM 86 */ 790 <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040>, /* SODIMM 92 */ 791 <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040>, /* SODIMM 90 */ 792 <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040>; /* SODIMM 88 */ 793 }; 794 795 pinctrl_lpspi2_cs2: lpspi2cs2grp { 796 fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21>; /* SODIMM 65 */ 797 }; 798 799 /* Colibri UART_B */ 800 pinctrl_lpuart0: lpuart0grp { 801 fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020>, /* SODIMM 36 */ 802 <IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020>, /* SODIMM 38 */ 803 <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020>, /* SODIMM 34 */ 804 <IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020>; /* SODIMM 32 */ 805 }; 806 807 /* Colibri UART_C */ 808 pinctrl_lpuart2: lpuart2grp { 809 fsl,pins = <IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020>, /* SODIMM 19 */ 810 <IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020>; /* SODIMM 21 */ 811 }; 812 813 /* Colibri UART_A */ 814 pinctrl_lpuart3: lpuart3grp { 815 fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>, /* SODIMM 33 */ 816 <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>; /* SODIMM 35 */ 817 }; 818 819 /* Colibri UART_A Control */ 820 pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { 821 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20>, /* SODIMM 23 */ 822 <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20>, /* SODIMM 25 */ 823 <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20>, /* SODIMM 27 */ 824 <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20>, /* SODIMM 29 */ 825 <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20>, /* SODIMM 31 */ 826 <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20>; /* SODIMM 37 */ 827 }; 828 829 /* On module wifi module */ 830 pinctrl_pcieb: pciebgrp { 831 fsl,pins = <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061>, /* SODIMM 178 */ 832 <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061>, /* SODIMM 94 */ 833 <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60>; /* SODIMM 81 */ 834 }; 835 836 /* Colibri PWM_A */ 837 pinctrl_pwm_a: pwmagrp { 838 /* both pins are connected together, reserve the unused CSI_D05 */ 839 fsl,pins = <IMX8QXP_CSI_D05_CI_PI_D07 0x61>, /* SODIMM 59 */ 840 <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60>; /* SODIMM 59 */ 841 }; 842 843 /* Colibri PWM_B */ 844 pinctrl_pwm_b: pwmbgrp { 845 fsl,pins = <IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60>; /* SODIMM 28 */ 846 }; 847 848 /* Colibri PWM_C */ 849 pinctrl_pwm_c: pwmcgrp { 850 fsl,pins = <IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60>; /* SODIMM 30 */ 851 }; 852 853 /* Colibri PWM_D */ 854 pinctrl_pwm_d: pwmdgrp { 855 /* both pins are connected together, reserve the unused CSI_D04 */ 856 fsl,pins = <IMX8QXP_CSI_D04_CI_PI_D06 0x61>, /* SODIMM 67 */ 857 <IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60>; /* SODIMM 67 */ 858 }; 859 860 /* On-module I2S */ 861 pinctrl_sai0: sai0grp { 862 fsl,pins = <IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040>, 863 <IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040>, 864 <IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040>, 865 <IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040>; 866 }; 867 868 /* Colibri Audio Analogue Microphone GND */ 869 pinctrl_sgtl5000: sgtl5000grp { 870 fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41>; 871 }; 872 873 /* On-module SGTL5000 clock */ 874 pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp { 875 fsl,pins = <IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21>; 876 }; 877 878 /* On-module USB interrupt */ 879 pinctrl_usb3503a: usb3503agrp { 880 fsl,pins = <IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61>; 881 }; 882 883 /* Colibri USB Client Cable Detect */ 884 pinctrl_usbc_det: usbcdetgrp { 885 fsl,pins = <IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040>; /* SODIMM 137 */ 886 }; 887 888 /* USB Host Power Enable */ 889 pinctrl_usbh1_reg: usbh1reggrp { 890 fsl,pins = <IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040>; /* SODIMM 129 */ 891 }; 892 893 /* On-module eMMC */ 894 pinctrl_usdhc1: usdhc1grp { 895 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 896 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>, 897 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>, 898 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>, 899 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>, 900 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>, 901 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>, 902 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>, 903 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>, 904 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>, 905 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>, 906 <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>; 907 }; 908 909 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 910 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 911 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>, 912 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>, 913 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>, 914 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>, 915 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>, 916 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>, 917 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>, 918 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>, 919 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>, 920 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>, 921 <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>; 922 }; 923 924 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 925 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 926 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>, 927 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>, 928 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>, 929 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>, 930 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>, 931 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>, 932 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>, 933 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>, 934 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>, 935 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>, 936 <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>; 937 }; 938 939 /* Colibri SD/MMC Card Detect */ 940 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 941 fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021>; /* SODIMM 43 */ 942 }; 943 944 pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { 945 fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60>; /* SODIMM 43 */ 946 }; 947 948 /* Colibri SD/MMC Card */ 949 pinctrl_usdhc2: usdhc2grp { 950 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */ 951 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */ 952 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */ 953 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */ 954 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */ 955 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */ 956 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>; 957 }; 958 959 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 960 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */ 961 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */ 962 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */ 963 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */ 964 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */ 965 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */ 966 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>; 967 }; 968 969 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 970 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */ 971 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */ 972 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */ 973 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */ 974 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */ 975 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */ 976 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>; 977 }; 978 979 pinctrl_usdhc2_sleep: usdhc2slpgrp { 980 fsl,pins = <IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60>, /* SODIMM 47 */ 981 <IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60>, /* SODIMM 190 */ 982 <IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60>, /* SODIMM 192 */ 983 <IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60>, /* SODIMM 49 */ 984 <IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60>, /* SODIMM 51 */ 985 <IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60>, /* SODIMM 53 */ 986 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>; 987 }; 988 989 pinctrl_wifi: wifigrp { 990 fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20>; 991 }; 992}; 993 994/* Delete peripherals which are not present on SOC, but are defined in imx8-ss-*.dtsi */ 995 996/delete-node/ &adc1; 997/delete-node/ &adc1_lpcg; 998/delete-node/ &dsp; 999/delete-node/ &dsp_lpcg; 1000