1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 */ 5 6#include <dt-bindings/clock/imx8ulp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/imx8ulp-power.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8ulp-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec; 21 gpio0 = &gpiod; 22 gpio1 = &gpioe; 23 gpio2 = &gpiof; 24 mmc0 = &usdhc0; 25 mmc1 = &usdhc1; 26 mmc2 = &usdhc2; 27 serial0 = &lpuart4; 28 serial1 = &lpuart5; 29 serial2 = &lpuart6; 30 serial3 = &lpuart7; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 A35_0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a35"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 next-level-cache = <&A35_L2>; 43 cpu-idle-states = <&cpu_sleep>; 44 }; 45 46 A35_1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a35"; 49 reg = <0x0 0x1>; 50 enable-method = "psci"; 51 next-level-cache = <&A35_L2>; 52 cpu-idle-states = <&cpu_sleep>; 53 }; 54 55 A35_L2: l2-cache0 { 56 compatible = "cache"; 57 cache-level = <2>; 58 cache-unified; 59 }; 60 61 idle-states { 62 entry-method = "psci"; 63 64 cpu_sleep: cpu-sleep { 65 compatible = "arm,idle-state"; 66 arm,psci-suspend-param = <0x0>; 67 local-timer-stop; 68 entry-latency-us = <1000>; 69 exit-latency-us = <700>; 70 min-residency-us = <2700>; 71 }; 72 }; 73 }; 74 75 gic: interrupt-controller@2d400000 { 76 compatible = "arm,gic-v3"; 77 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ 78 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 79 #interrupt-cells = <3>; 80 interrupt-controller; 81 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 82 }; 83 84 pmu { 85 compatible = "arm,cortex-a35-pmu"; 86 interrupt-parent = <&gic>; 87 interrupts = <GIC_PPI 7 88 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 89 interrupt-affinity = <&A35_0>, <&A35_1>; 90 }; 91 92 psci { 93 compatible = "arm,psci-1.0"; 94 method = "smc"; 95 }; 96 97 thermal-zones { 98 cpu-thermal { 99 polling-delay-passive = <250>; 100 polling-delay = <2000>; 101 thermal-sensors = <&scmi_sensor 0>; 102 103 trips { 104 cpu_alert0: trip0 { 105 temperature = <85000>; 106 hysteresis = <2000>; 107 type = "passive"; 108 }; 109 110 cpu_crit0: trip1 { 111 temperature = <95000>; 112 hysteresis = <2000>; 113 type = "critical"; 114 }; 115 }; 116 }; 117 }; 118 119 timer { 120 compatible = "arm,armv8-timer"; 121 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 122 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 123 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 124 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 125 }; 126 127 frosc: clock-frosc { 128 compatible = "fixed-clock"; 129 clock-frequency = <192000000>; 130 clock-output-names = "frosc"; 131 #clock-cells = <0>; 132 }; 133 134 lposc: clock-lposc { 135 compatible = "fixed-clock"; 136 clock-frequency = <1000000>; 137 clock-output-names = "lposc"; 138 #clock-cells = <0>; 139 }; 140 141 rosc: clock-rosc { 142 compatible = "fixed-clock"; 143 clock-frequency = <32768>; 144 clock-output-names = "rosc"; 145 #clock-cells = <0>; 146 }; 147 148 sosc: clock-sosc { 149 compatible = "fixed-clock"; 150 clock-frequency = <24000000>; 151 clock-output-names = "sosc"; 152 #clock-cells = <0>; 153 }; 154 155 sram@2201f000 { 156 compatible = "mmio-sram"; 157 reg = <0x0 0x2201f000 0x0 0x1000>; 158 159 #address-cells = <1>; 160 #size-cells = <1>; 161 ranges = <0 0x0 0x2201f000 0x1000>; 162 163 scmi_buf: scmi-sram-section@0 { 164 compatible = "arm,scmi-shmem"; 165 reg = <0x0 0x400>; 166 }; 167 }; 168 169 firmware { 170 scmi { 171 compatible = "arm,scmi-smc"; 172 arm,smc-id = <0xc20000fe>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 shmem = <&scmi_buf>; 176 177 scmi_devpd: protocol@11 { 178 reg = <0x11>; 179 #power-domain-cells = <1>; 180 }; 181 182 scmi_sensor: protocol@15 { 183 reg = <0x15>; 184 #thermal-sensor-cells = <1>; 185 }; 186 }; 187 }; 188 189 cm33: remoteproc-cm33 { 190 compatible = "fsl,imx8ulp-cm33"; 191 status = "disabled"; 192 }; 193 194 soc: soc@0 { 195 compatible = "simple-bus"; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0x0 0x0 0x0 0x40000000>, 199 <0x60000000 0x0 0x60000000 0x1000000>; 200 201 s4muap: mailbox@27020000 { 202 compatible = "fsl,imx8ulp-mu-s4"; 203 reg = <0x27020000 0x10000>; 204 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 205 #mbox-cells = <2>; 206 }; 207 208 per_bridge3: bus@29000000 { 209 compatible = "simple-bus"; 210 reg = <0x29000000 0x800000>; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges; 214 215 mu: mailbox@29220000 { 216 compatible = "fsl,imx8ulp-mu"; 217 reg = <0x29220000 0x10000>; 218 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 219 #mbox-cells = <2>; 220 status = "disabled"; 221 }; 222 223 mu3: mailbox@29230000 { 224 compatible = "fsl,imx8ulp-mu"; 225 reg = <0x29230000 0x10000>; 226 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&pcc3 IMX8ULP_CLK_MU3_A>; 228 #mbox-cells = <2>; 229 status = "disabled"; 230 }; 231 232 wdog3: watchdog@292a0000 { 233 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; 234 reg = <0x292a0000 0x10000>; 235 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 237 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 238 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; 239 timeout-sec = <40>; 240 }; 241 242 cgc1: clock-controller@292c0000 { 243 compatible = "fsl,imx8ulp-cgc1"; 244 reg = <0x292c0000 0x10000>; 245 #clock-cells = <1>; 246 }; 247 248 pcc3: clock-controller@292d0000 { 249 compatible = "fsl,imx8ulp-pcc3"; 250 reg = <0x292d0000 0x10000>; 251 #clock-cells = <1>; 252 #reset-cells = <1>; 253 }; 254 255 crypto: crypto@292e0000 { 256 compatible = "fsl,sec-v4.0"; 257 reg = <0x292e0000 0x10000>; 258 ranges = <0 0x292e0000 0x10000>; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 262 sec_jr0: jr@1000 { 263 compatible = "fsl,sec-v4.0-job-ring"; 264 reg = <0x1000 0x1000>; 265 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 266 }; 267 268 sec_jr1: jr@2000 { 269 compatible = "fsl,sec-v4.0-job-ring"; 270 reg = <0x2000 0x1000>; 271 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 272 }; 273 274 sec_jr2: jr@3000 { 275 compatible = "fsl,sec-v4.0-job-ring"; 276 reg = <0x3000 0x1000>; 277 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 278 }; 279 280 sec_jr3: jr@4000 { 281 compatible = "fsl,sec-v4.0-job-ring"; 282 reg = <0x4000 0x1000>; 283 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 284 }; 285 }; 286 287 tpm5: tpm@29340000 { 288 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; 289 reg = <0x29340000 0x1000>; 290 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&pcc3 IMX8ULP_CLK_TPM5>, 292 <&pcc3 IMX8ULP_CLK_TPM5>; 293 clock-names = "ipg", "per"; 294 status = "disabled"; 295 }; 296 297 lpi2c4: i2c@29370000 { 298 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 299 reg = <0x29370000 0x10000>; 300 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, 302 <&pcc3 IMX8ULP_CLK_LPI2C4>; 303 clock-names = "per", "ipg"; 304 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; 305 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 306 assigned-clock-rates = <48000000>; 307 status = "disabled"; 308 }; 309 310 lpi2c5: i2c@29380000 { 311 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 312 reg = <0x29380000 0x10000>; 313 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, 315 <&pcc3 IMX8ULP_CLK_LPI2C5>; 316 clock-names = "per", "ipg"; 317 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; 318 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 319 assigned-clock-rates = <48000000>; 320 status = "disabled"; 321 }; 322 323 lpuart4: serial@29390000 { 324 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 325 reg = <0x29390000 0x1000>; 326 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; 328 clock-names = "ipg"; 329 status = "disabled"; 330 }; 331 332 lpuart5: serial@293a0000 { 333 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 334 reg = <0x293a0000 0x1000>; 335 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; 337 clock-names = "ipg"; 338 status = "disabled"; 339 }; 340 341 lpspi4: spi@293b0000 { 342 #address-cells = <1>; 343 #size-cells = <0>; 344 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 345 reg = <0x293b0000 0x10000>; 346 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, 348 <&pcc3 IMX8ULP_CLK_LPSPI4>; 349 clock-names = "per", "ipg"; 350 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; 351 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 352 assigned-clock-rates = <48000000>; 353 status = "disabled"; 354 }; 355 356 lpspi5: spi@293c0000 { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 360 reg = <0x293c0000 0x10000>; 361 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, 363 <&pcc3 IMX8ULP_CLK_LPSPI5>; 364 clock-names = "per", "ipg"; 365 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; 366 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 367 assigned-clock-rates = <48000000>; 368 status = "disabled"; 369 }; 370 }; 371 372 per_bridge4: bus@29800000 { 373 compatible = "simple-bus"; 374 reg = <0x29800000 0x800000>; 375 #address-cells = <1>; 376 #size-cells = <1>; 377 ranges; 378 379 pcc4: clock-controller@29800000 { 380 compatible = "fsl,imx8ulp-pcc4"; 381 reg = <0x29800000 0x10000>; 382 #clock-cells = <1>; 383 #reset-cells = <1>; 384 }; 385 386 flexspi2: spi@29810000 { 387 compatible = "nxp,imx8ulp-fspi"; 388 reg = <0x29810000 0x10000>, <0x60000000 0x10000000>; 389 reg-names = "fspi_base", "fspi_mmap"; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>, 394 <&pcc4 IMX8ULP_CLK_FLEXSPI2>; 395 clock-names = "fspi_en", "fspi"; 396 assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>; 397 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 398 status = "disabled"; 399 }; 400 401 lpi2c6: i2c@29840000 { 402 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 403 reg = <0x29840000 0x10000>; 404 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, 406 <&pcc4 IMX8ULP_CLK_LPI2C6>; 407 clock-names = "per", "ipg"; 408 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; 409 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 410 assigned-clock-rates = <48000000>; 411 status = "disabled"; 412 }; 413 414 lpi2c7: i2c@29850000 { 415 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 416 reg = <0x29850000 0x10000>; 417 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, 419 <&pcc4 IMX8ULP_CLK_LPI2C7>; 420 clock-names = "per", "ipg"; 421 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; 422 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 423 assigned-clock-rates = <48000000>; 424 status = "disabled"; 425 }; 426 427 lpuart6: serial@29860000 { 428 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 429 reg = <0x29860000 0x1000>; 430 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; 432 clock-names = "ipg"; 433 status = "disabled"; 434 }; 435 436 lpuart7: serial@29870000 { 437 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 438 reg = <0x29870000 0x1000>; 439 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; 441 clock-names = "ipg"; 442 status = "disabled"; 443 }; 444 445 iomuxc1: pinctrl@298c0000 { 446 compatible = "fsl,imx8ulp-iomuxc1"; 447 reg = <0x298c0000 0x10000>; 448 }; 449 450 usdhc0: mmc@298d0000 { 451 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 452 reg = <0x298d0000 0x10000>; 453 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 455 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, 456 <&pcc4 IMX8ULP_CLK_USDHC0>; 457 clock-names = "ipg", "ahb", "per"; 458 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; 459 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>, 460 <&pcc4 IMX8ULP_CLK_USDHC0>; 461 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>; 462 assigned-clock-rates = <389283840>, <389283840>; 463 fsl,tuning-start-tap = <20>; 464 fsl,tuning-step = <2>; 465 bus-width = <4>; 466 status = "disabled"; 467 }; 468 469 usdhc1: mmc@298e0000 { 470 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 471 reg = <0x298e0000 0x10000>; 472 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 474 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 475 <&pcc4 IMX8ULP_CLK_USDHC1>; 476 clock-names = "ipg", "ahb", "per"; 477 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; 478 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, 479 <&pcc4 IMX8ULP_CLK_USDHC1>; 480 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 481 assigned-clock-rates = <194641920>, <194641920>; 482 fsl,tuning-start-tap = <20>; 483 fsl,tuning-step = <2>; 484 bus-width = <4>; 485 status = "disabled"; 486 }; 487 488 usdhc2: mmc@298f0000 { 489 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 490 reg = <0x298f0000 0x10000>; 491 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 493 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 494 <&pcc4 IMX8ULP_CLK_USDHC2>; 495 clock-names = "ipg", "ahb", "per"; 496 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 497 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, 498 <&pcc4 IMX8ULP_CLK_USDHC2>; 499 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 500 assigned-clock-rates = <194641920>, <194641920>; 501 fsl,tuning-start-tap = <20>; 502 fsl,tuning-step = <2>; 503 bus-width = <4>; 504 status = "disabled"; 505 }; 506 507 usbotg1: usb@29900000 { 508 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; 509 reg = <0x29900000 0x200>; 510 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&pcc4 IMX8ULP_CLK_USB0>; 512 power-domains = <&scmi_devpd IMX8ULP_PD_USB0>; 513 phys = <&usbphy1>; 514 fsl,usbmisc = <&usbmisc1 0>; 515 ahb-burst-config = <0x0>; 516 tx-burst-size-dword = <0x8>; 517 rx-burst-size-dword = <0x8>; 518 status = "disabled"; 519 }; 520 521 usbmisc1: usbmisc@29900200 { 522 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc", 523 "fsl,imx6q-usbmisc"; 524 reg = <0x29900200 0x200>; 525 #index-cells = <1>; 526 status = "disabled"; 527 }; 528 529 usbphy1: usb-phy@29910000 { 530 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; 531 reg = <0x29910000 0x10000>; 532 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>; 534 #phy-cells = <0>; 535 status = "disabled"; 536 }; 537 538 usbotg2: usb@29920000 { 539 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; 540 reg = <0x29920000 0x200>; 541 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&pcc4 IMX8ULP_CLK_USB1>; 543 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 544 phys = <&usbphy2>; 545 fsl,usbmisc = <&usbmisc2 0>; 546 ahb-burst-config = <0x0>; 547 tx-burst-size-dword = <0x8>; 548 rx-burst-size-dword = <0x8>; 549 status = "disabled"; 550 }; 551 552 usbmisc2: usbmisc@29920200 { 553 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc", 554 "fsl,imx6q-usbmisc"; 555 reg = <0x29920200 0x200>; 556 #index-cells = <1>; 557 status = "disabled"; 558 }; 559 560 usbphy2: usb-phy@29930000 { 561 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; 562 reg = <0x29930000 0x10000>; 563 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>; 565 #phy-cells = <0>; 566 status = "disabled"; 567 }; 568 569 fec: ethernet@29950000 { 570 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec"; 571 reg = <0x29950000 0x10000>; 572 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "int0"; 574 fsl,num-tx-queues = <1>; 575 fsl,num-rx-queues = <1>; 576 status = "disabled"; 577 }; 578 }; 579 580 gpioe: gpio@2d000000 { 581 compatible = "fsl,imx8ulp-gpio"; 582 reg = <0x2d000000 0x1000>; 583 gpio-controller; 584 #gpio-cells = <2>; 585 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, 590 <&pcc4 IMX8ULP_CLK_PCTLE>; 591 clock-names = "gpio", "port"; 592 gpio-ranges = <&iomuxc1 0 32 24>; 593 }; 594 595 gpiof: gpio@2d010000 { 596 compatible = "fsl,imx8ulp-gpio"; 597 reg = <0x2d010000 0x1000>; 598 gpio-controller; 599 #gpio-cells = <2>; 600 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, 605 <&pcc4 IMX8ULP_CLK_PCTLF>; 606 clock-names = "gpio", "port"; 607 gpio-ranges = <&iomuxc1 0 64 32>; 608 }; 609 610 per_bridge5: bus@2d800000 { 611 compatible = "simple-bus"; 612 reg = <0x2d800000 0x800000>; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 ranges; 616 617 cgc2: clock-controller@2da60000 { 618 compatible = "fsl,imx8ulp-cgc2"; 619 reg = <0x2da60000 0x10000>; 620 #clock-cells = <1>; 621 }; 622 623 pcc5: clock-controller@2da70000 { 624 compatible = "fsl,imx8ulp-pcc5"; 625 reg = <0x2da70000 0x10000>; 626 #clock-cells = <1>; 627 #reset-cells = <1>; 628 }; 629 }; 630 631 gpiod: gpio@2e200000 { 632 compatible = "fsl,imx8ulp-gpio"; 633 reg = <0x2e200000 0x1000>; 634 gpio-controller; 635 #gpio-cells = <2>; 636 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 638 interrupt-controller; 639 #interrupt-cells = <2>; 640 clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, 641 <&pcc5 IMX8ULP_CLK_RGPIOD>; 642 clock-names = "gpio", "port"; 643 gpio-ranges = <&iomuxc1 0 0 24>; 644 }; 645 }; 646}; 647