1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2020 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/clock/imx8-lpcg.h> 10#include <dt-bindings/firmware/imx/rsrc.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/pinctrl/pads-imx8qxp.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec1; 24 ethernet1 = &fec2; 25 gpio0 = &lsio_gpio0; 26 gpio1 = &lsio_gpio1; 27 gpio2 = &lsio_gpio2; 28 gpio3 = &lsio_gpio3; 29 gpio4 = &lsio_gpio4; 30 gpio5 = &lsio_gpio5; 31 gpio6 = &lsio_gpio6; 32 gpio7 = &lsio_gpio7; 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 mu0 = &lsio_mu0; 41 mu1 = &lsio_mu1; 42 mu2 = &lsio_mu2; 43 mu3 = &lsio_mu3; 44 mu4 = &lsio_mu4; 45 serial0 = &lpuart0; 46 serial1 = &lpuart1; 47 serial2 = &lpuart2; 48 serial3 = &lpuart3; 49 vpu-core0 = &vpu_core0; 50 vpu-core1 = &vpu_core1; 51 }; 52 53 cpus { 54 #address-cells = <2>; 55 #size-cells = <0>; 56 57 /* We have 1 clusters with 4 Cortex-A35 cores */ 58 A35_0: cpu@0 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a35"; 61 reg = <0x0 0x0>; 62 enable-method = "psci"; 63 i-cache-size = <0x8000>; 64 i-cache-line-size = <64>; 65 i-cache-sets = <256>; 66 d-cache-size = <0x8000>; 67 d-cache-line-size = <64>; 68 d-cache-sets = <128>; 69 next-level-cache = <&A35_L2>; 70 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 71 operating-points-v2 = <&a35_opp_table>; 72 #cooling-cells = <2>; 73 }; 74 75 A35_1: cpu@1 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a35"; 78 reg = <0x0 0x1>; 79 enable-method = "psci"; 80 i-cache-size = <0x8000>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <256>; 83 d-cache-size = <0x8000>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <128>; 86 next-level-cache = <&A35_L2>; 87 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 88 operating-points-v2 = <&a35_opp_table>; 89 #cooling-cells = <2>; 90 }; 91 92 A35_2: cpu@2 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a35"; 95 reg = <0x0 0x2>; 96 enable-method = "psci"; 97 i-cache-size = <0x8000>; 98 i-cache-line-size = <64>; 99 i-cache-sets = <256>; 100 d-cache-size = <0x8000>; 101 d-cache-line-size = <64>; 102 d-cache-sets = <128>; 103 next-level-cache = <&A35_L2>; 104 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 105 operating-points-v2 = <&a35_opp_table>; 106 #cooling-cells = <2>; 107 }; 108 109 A35_3: cpu@3 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a35"; 112 reg = <0x0 0x3>; 113 enable-method = "psci"; 114 i-cache-size = <0x8000>; 115 i-cache-line-size = <64>; 116 i-cache-sets = <256>; 117 d-cache-size = <0x8000>; 118 d-cache-line-size = <64>; 119 d-cache-sets = <128>; 120 next-level-cache = <&A35_L2>; 121 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 122 operating-points-v2 = <&a35_opp_table>; 123 #cooling-cells = <2>; 124 }; 125 126 A35_L2: l2-cache0 { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 cache-size = <0x80000>; 131 cache-line-size = <64>; 132 cache-sets = <1024>; 133 }; 134 }; 135 136 a35_opp_table: opp-table { 137 compatible = "operating-points-v2"; 138 opp-shared; 139 140 opp-900000000 { 141 opp-hz = /bits/ 64 <900000000>; 142 opp-microvolt = <1000000>; 143 clock-latency-ns = <150000>; 144 }; 145 146 opp-1200000000 { 147 opp-hz = /bits/ 64 <1200000000>; 148 opp-microvolt = <1100000>; 149 clock-latency-ns = <150000>; 150 opp-suspend; 151 }; 152 }; 153 154 gic: interrupt-controller@51a00000 { 155 compatible = "arm,gic-v3"; 156 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 157 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 158 #interrupt-cells = <3>; 159 interrupt-controller; 160 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 161 }; 162 163 reserved-memory { 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges; 167 168 decoder_boot: decoder-boot@84000000 { 169 reg = <0 0x84000000 0 0x2000000>; 170 no-map; 171 }; 172 173 encoder_boot: encoder-boot@86000000 { 174 reg = <0 0x86000000 0 0x200000>; 175 no-map; 176 }; 177 178 decoder_rpc: decoder-rpc@92000000 { 179 reg = <0 0x92000000 0 0x100000>; 180 no-map; 181 }; 182 183 dsp_reserved: dsp@92400000 { 184 reg = <0 0x92400000 0 0x2000000>; 185 no-map; 186 status = "disabled"; 187 }; 188 189 encoder_rpc: encoder-rpc@94400000 { 190 reg = <0 0x94400000 0 0x700000>; 191 no-map; 192 }; 193 }; 194 195 pmu { 196 compatible = "arm,cortex-a35-pmu"; 197 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 198 }; 199 200 psci { 201 compatible = "arm,psci-1.0"; 202 method = "smc"; 203 }; 204 205 system-controller { 206 compatible = "fsl,imx-scu"; 207 mbox-names = "tx0", 208 "rx0", 209 "gip3"; 210 mboxes = <&lsio_mu1 0 0 211 &lsio_mu1 1 0 212 &lsio_mu1 3 3>; 213 214 pd: power-controller { 215 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 216 #power-domain-cells = <1>; 217 }; 218 219 clk: clock-controller { 220 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 221 #clock-cells = <2>; 222 }; 223 224 iomuxc: pinctrl { 225 compatible = "fsl,imx8qxp-iomuxc"; 226 }; 227 228 ocotp: ocotp { 229 compatible = "fsl,imx8qxp-scu-ocotp"; 230 #address-cells = <1>; 231 #size-cells = <1>; 232 }; 233 234 scu_key: keys { 235 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 236 linux,keycodes = <KEY_POWER>; 237 status = "disabled"; 238 }; 239 240 rtc: rtc { 241 compatible = "fsl,imx8qxp-sc-rtc"; 242 }; 243 244 watchdog { 245 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 246 timeout-sec = <60>; 247 }; 248 249 tsens: thermal-sensor { 250 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 251 #thermal-sensor-cells = <1>; 252 }; 253 }; 254 255 timer { 256 compatible = "arm,armv8-timer"; 257 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 259 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 260 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 261 }; 262 263 clk_dummy: clock-dummy { 264 compatible = "fixed-clock"; 265 #clock-cells = <0>; 266 clock-frequency = <0>; 267 clock-output-names = "clk_dummy"; 268 }; 269 270 xtal32k: clock-xtal32k { 271 compatible = "fixed-clock"; 272 #clock-cells = <0>; 273 clock-frequency = <32768>; 274 clock-output-names = "xtal_32KHz"; 275 }; 276 277 xtal24m: clock-xtal24m { 278 compatible = "fixed-clock"; 279 #clock-cells = <0>; 280 clock-frequency = <24000000>; 281 clock-output-names = "xtal_24MHz"; 282 }; 283 284 thermal_zones: thermal-zones { 285 cpu0-thermal { 286 polling-delay-passive = <250>; 287 polling-delay = <2000>; 288 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 289 290 trips { 291 cpu_alert0: trip0 { 292 temperature = <107000>; 293 hysteresis = <2000>; 294 type = "passive"; 295 }; 296 297 cpu_crit0: trip1 { 298 temperature = <127000>; 299 hysteresis = <2000>; 300 type = "critical"; 301 }; 302 }; 303 304 cooling-maps { 305 map0 { 306 trip = <&cpu_alert0>; 307 cooling-device = 308 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 309 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 310 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 311 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 312 }; 313 }; 314 }; 315 }; 316 317 /* sorted in register address */ 318 #include "imx8-ss-img.dtsi" 319 #include "imx8-ss-vpu.dtsi" 320 #include "imx8-ss-cm40.dtsi" 321 #include "imx8-ss-gpu0.dtsi" 322 #include "imx8-ss-adma.dtsi" 323 #include "imx8-ss-conn.dtsi" 324 #include "imx8-ss-ddr.dtsi" 325 #include "imx8-ss-lsio.dtsi" 326}; 327 328#include "imx8qxp-ss-img.dtsi" 329#include "imx8qxp-ss-vpu.dtsi" 330#include "imx8qxp-ss-adma.dtsi" 331#include "imx8qxp-ss-conn.dtsi" 332#include "imx8qxp-ss-lsio.dtsi" 333