1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2020 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/clock/imx8-lpcg.h> 10#include <dt-bindings/firmware/imx/rsrc.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/pinctrl/pads-imx8qxp.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec1; 24 ethernet1 = &fec2; 25 gpio0 = &lsio_gpio0; 26 gpio1 = &lsio_gpio1; 27 gpio2 = &lsio_gpio2; 28 gpio3 = &lsio_gpio3; 29 gpio4 = &lsio_gpio4; 30 gpio5 = &lsio_gpio5; 31 gpio6 = &lsio_gpio6; 32 gpio7 = &lsio_gpio7; 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 mu0 = &lsio_mu0; 41 mu1 = &lsio_mu1; 42 mu2 = &lsio_mu2; 43 mu3 = &lsio_mu3; 44 mu4 = &lsio_mu4; 45 serial0 = &lpuart0; 46 serial1 = &lpuart1; 47 serial2 = &lpuart2; 48 serial3 = &lpuart3; 49 spi0 = &lpspi0; 50 spi1 = &lpspi1; 51 spi2 = &lpspi2; 52 spi3 = &lpspi3; 53 vpu-core0 = &vpu_core0; 54 vpu-core1 = &vpu_core1; 55 }; 56 57 cpus { 58 #address-cells = <2>; 59 #size-cells = <0>; 60 61 /* We have 1 clusters with 4 Cortex-A35 cores */ 62 A35_0: cpu@0 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a35"; 65 reg = <0x0 0x0>; 66 enable-method = "psci"; 67 i-cache-size = <0x8000>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <256>; 70 d-cache-size = <0x8000>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&A35_L2>; 74 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 75 operating-points-v2 = <&a35_opp_table>; 76 #cooling-cells = <2>; 77 }; 78 79 A35_1: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a35"; 82 reg = <0x0 0x1>; 83 enable-method = "psci"; 84 i-cache-size = <0x8000>; 85 i-cache-line-size = <64>; 86 i-cache-sets = <256>; 87 d-cache-size = <0x8000>; 88 d-cache-line-size = <64>; 89 d-cache-sets = <128>; 90 next-level-cache = <&A35_L2>; 91 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 92 operating-points-v2 = <&a35_opp_table>; 93 #cooling-cells = <2>; 94 }; 95 96 A35_2: cpu@2 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a35"; 99 reg = <0x0 0x2>; 100 enable-method = "psci"; 101 i-cache-size = <0x8000>; 102 i-cache-line-size = <64>; 103 i-cache-sets = <256>; 104 d-cache-size = <0x8000>; 105 d-cache-line-size = <64>; 106 d-cache-sets = <128>; 107 next-level-cache = <&A35_L2>; 108 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 109 operating-points-v2 = <&a35_opp_table>; 110 #cooling-cells = <2>; 111 }; 112 113 A35_3: cpu@3 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a35"; 116 reg = <0x0 0x3>; 117 enable-method = "psci"; 118 i-cache-size = <0x8000>; 119 i-cache-line-size = <64>; 120 i-cache-sets = <256>; 121 d-cache-size = <0x8000>; 122 d-cache-line-size = <64>; 123 d-cache-sets = <128>; 124 next-level-cache = <&A35_L2>; 125 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 126 operating-points-v2 = <&a35_opp_table>; 127 #cooling-cells = <2>; 128 }; 129 130 A35_L2: l2-cache0 { 131 compatible = "cache"; 132 cache-level = <2>; 133 cache-unified; 134 cache-size = <0x80000>; 135 cache-line-size = <64>; 136 cache-sets = <1024>; 137 }; 138 }; 139 140 a35_opp_table: opp-table { 141 compatible = "operating-points-v2"; 142 opp-shared; 143 144 opp-900000000 { 145 opp-hz = /bits/ 64 <900000000>; 146 opp-microvolt = <1000000>; 147 clock-latency-ns = <150000>; 148 }; 149 150 opp-1200000000 { 151 opp-hz = /bits/ 64 <1200000000>; 152 opp-microvolt = <1100000>; 153 clock-latency-ns = <150000>; 154 opp-suspend; 155 }; 156 }; 157 158 gic: interrupt-controller@51a00000 { 159 compatible = "arm,gic-v3"; 160 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 161 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 162 #address-cells = <0>; 163 #interrupt-cells = <3>; 164 interrupt-controller; 165 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 166 }; 167 168 reserved-memory { 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 173 decoder_boot: decoder-boot@84000000 { 174 reg = <0 0x84000000 0 0x2000000>; 175 no-map; 176 }; 177 178 encoder_boot: encoder-boot@86000000 { 179 reg = <0 0x86000000 0 0x200000>; 180 no-map; 181 }; 182 183 decoder_rpc: decoder-rpc@92000000 { 184 reg = <0 0x92000000 0 0x100000>; 185 no-map; 186 }; 187 188 dsp_reserved: dsp@92400000 { 189 reg = <0 0x92400000 0 0x2000000>; 190 no-map; 191 status = "disabled"; 192 }; 193 194 encoder_rpc: encoder-rpc@94400000 { 195 reg = <0 0x94400000 0 0x700000>; 196 no-map; 197 }; 198 }; 199 200 pmu { 201 compatible = "arm,cortex-a35-pmu"; 202 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 203 }; 204 205 psci { 206 compatible = "arm,psci-1.0"; 207 method = "smc"; 208 }; 209 210 system-controller { 211 compatible = "fsl,imx-scu"; 212 mbox-names = "tx0", 213 "rx0", 214 "gip3"; 215 mboxes = <&lsio_mu1 0 0 216 &lsio_mu1 1 0 217 &lsio_mu1 3 3>; 218 219 pd: power-controller { 220 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 221 #power-domain-cells = <1>; 222 }; 223 224 clk: clock-controller { 225 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 226 #clock-cells = <2>; 227 }; 228 229 iomuxc: pinctrl { 230 compatible = "fsl,imx8qxp-iomuxc"; 231 }; 232 233 ocotp: ocotp { 234 compatible = "fsl,imx8qxp-scu-ocotp"; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 }; 238 239 scu_key: keys { 240 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 241 linux,keycodes = <KEY_POWER>; 242 status = "disabled"; 243 }; 244 245 scu_reset: reset-controller { 246 compatible = "fsl,imx-scu-reset"; 247 #reset-cells = <1>; 248 }; 249 250 rtc: rtc { 251 compatible = "fsl,imx8qxp-sc-rtc"; 252 }; 253 254 watchdog { 255 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 256 timeout-sec = <60>; 257 }; 258 259 tsens: thermal-sensor { 260 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 261 #thermal-sensor-cells = <1>; 262 }; 263 }; 264 265 timer { 266 compatible = "arm,armv8-timer"; 267 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 268 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 269 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 270 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 271 }; 272 273 clk_dummy: clock-dummy { 274 compatible = "fixed-clock"; 275 #clock-cells = <0>; 276 clock-frequency = <0>; 277 clock-output-names = "clk_dummy"; 278 }; 279 280 xtal32k: clock-xtal32k { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <32768>; 284 clock-output-names = "xtal_32KHz"; 285 }; 286 287 xtal24m: clock-xtal24m { 288 compatible = "fixed-clock"; 289 #clock-cells = <0>; 290 clock-frequency = <24000000>; 291 clock-output-names = "xtal_24MHz"; 292 }; 293 294 thermal_zones: thermal-zones { 295 cpu0-thermal { 296 polling-delay-passive = <250>; 297 polling-delay = <2000>; 298 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 299 300 trips { 301 cpu_alert0: trip0 { 302 temperature = <107000>; 303 hysteresis = <2000>; 304 type = "passive"; 305 }; 306 307 cpu_crit0: trip1 { 308 temperature = <127000>; 309 hysteresis = <2000>; 310 type = "critical"; 311 }; 312 }; 313 314 cooling-maps { 315 map0 { 316 trip = <&cpu_alert0>; 317 cooling-device = 318 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 319 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 320 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 321 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 322 }; 323 }; 324 }; 325 }; 326 327 /* sorted in register address */ 328 #include "imx8-ss-img.dtsi" 329 #include "imx8-ss-vpu.dtsi" 330 #include "imx8-ss-security.dtsi" 331 #include "imx8-ss-cm40.dtsi" 332 #include "imx8-ss-gpu0.dtsi" 333 #include "imx8-ss-adma.dtsi" 334 #include "imx8-ss-conn.dtsi" 335 #include "imx8-ss-ddr.dtsi" 336 #include "imx8-ss-lsio.dtsi" 337 #include "imx8-ss-hsio.dtsi" 338}; 339 340#include "imx8qxp-ss-img.dtsi" 341#include "imx8qxp-ss-vpu.dtsi" 342#include "imx8qxp-ss-security.dtsi" 343#include "imx8qxp-ss-adma.dtsi" 344#include "imx8qxp-ss-conn.dtsi" 345#include "imx8qxp-ss-lsio.dtsi" 346#include "imx8qxp-ss-hsio.dtsi" 347