1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2021 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7&csi1_pxl_lpcg { 8 status = "disabled"; 9}; 10 11&csi1_core_lpcg { 12 status = "disabled"; 13}; 14 15&csi1_esc_lpcg { 16 status = "disabled"; 17}; 18 19&gpio0_mipi_csi1 { 20 status = "disabled"; 21}; 22 23&i2c_mipi_csi1 { 24 status = "disabled"; 25}; 26 27&irqsteer_csi1 { 28 status = "disabled"; 29}; 30 31&isi { 32 compatible = "fsl,imx8qxp-isi"; 33 reg = <0x58100000 0x60000>; 34 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 40 clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, 41 <&pdma1_lpcg IMX_LPCG_CLK_0>, 42 <&pdma2_lpcg IMX_LPCG_CLK_0>, 43 <&pdma3_lpcg IMX_LPCG_CLK_0>, 44 <&pdma4_lpcg IMX_LPCG_CLK_0>, 45 <&pdma5_lpcg IMX_LPCG_CLK_0>; 46 clock-names = "per0", "per1", "per2", "per3", "per4", "per5"; 47 power-domains = <&pd IMX_SC_R_ISI_CH0>, 48 <&pd IMX_SC_R_ISI_CH1>, 49 <&pd IMX_SC_R_ISI_CH2>, 50 <&pd IMX_SC_R_ISI_CH3>, 51 <&pd IMX_SC_R_ISI_CH4>, 52 <&pd IMX_SC_R_ISI_CH5>; 53 54 ports { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 port@2 { 59 reg = <2>; 60 61 isi_in_2: endpoint { 62 remote-endpoint = <&mipi_csi0_out>; 63 }; 64 }; 65 }; 66}; 67 68&mipi_csi_0 { 69 ports { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 port@0 { 74 reg = <0>; 75 }; 76 77 port@1 { 78 reg = <1>; 79 80 mipi_csi0_out: endpoint { 81 remote-endpoint = <&isi_in_2>; 82 }; 83 }; 84 }; 85}; 86 87&jpegdec { 88 compatible = "nxp,imx8qxp-jpgdec"; 89}; 90 91&jpegenc { 92 compatible = "nxp,imx8qxp-jpgenc"; 93}; 94 95&mipi_csi_1 { 96 status = "disabled"; 97}; 98