1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2024 NXP 4 * Richard Zhu <hongxing.zhu@nxp.com> 5 */ 6 7&hsio_subsys { 8 phyx1_lpcg: clock-controller@5f090000 { 9 compatible = "fsl,imx8qxp-lpcg"; 10 reg = <0x5f090000 0x10000>; 11 clocks = <&hsio_refb_clk>, <&hsio_per_clk>, 12 <&hsio_per_clk>, <&hsio_per_clk>; 13 #clock-cells = <1>; 14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 15 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>; 16 clock-output-names = "hsio_phyx1_pclk", 17 "hsio_phyx1_epcs_tx_clk", 18 "hsio_phyx1_epcs_rx_clk", 19 "hsio_phyx1_apb_clk"; 20 power-domains = <&pd IMX_SC_R_SERDES_1>; 21 }; 22 23 hsio_phy: phy@5f1a0000 { 24 compatible = "fsl,imx8qxp-hsio"; 25 reg = <0x5f1a0000 0x10000>, 26 <0x5f120000 0x10000>, 27 <0x5f140000 0x10000>, 28 <0x5f160000 0x10000>; 29 reg-names = "reg", "phy", "ctrl", "misc"; 30 clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>, 31 <&phyx1_lpcg IMX_LPCG_CLK_1>, 32 <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, 33 <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, 34 <&misc_crr5_lpcg IMX_LPCG_CLK_4>; 35 clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", 36 "misc_crr"; 37 #phy-cells = <3>; 38 power-domains = <&pd IMX_SC_R_SERDES_1>; 39 status = "disabled"; 40 }; 41}; 42