1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017~2018 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8qxp.dtsi" 9#include <dt-bindings/usb/pd.h> 10 11/ { 12 model = "Freescale i.MX8QXP MEK"; 13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 14 15 bt_sco_codec: audio-codec-bt { 16 compatible = "linux,bt-sco"; 17 #sound-dai-cells = <1>; 18 }; 19 20 chosen { 21 stdout-path = &lpuart0; 22 }; 23 24 imx8x_cm4: imx8x-cm4 { 25 compatible = "fsl,imx8qxp-cm4"; 26 mbox-names = "tx", "rx", "rxdb"; 27 mboxes = <&lsio_mu5 0 1 28 &lsio_mu5 1 1 29 &lsio_mu5 3 1>; 30 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 31 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 32 power-domains = <&pd IMX_SC_R_M4_0_PID0>, 33 <&pd IMX_SC_R_M4_0_MU_1A>; 34 fsl,entry-address = <0x34fe0000>; 35 fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 36 }; 37 38 memory@80000000 { 39 device_type = "memory"; 40 reg = <0x00000000 0x80000000 0 0x40000000>; 41 }; 42 43 reserved-memory { 44 dsp_vdev0vring0: memory@942f0000 { 45 reg = <0 0x942f0000 0 0x8000>; 46 no-map; 47 }; 48 49 dsp_vdev0vring1: memory@942f8000 { 50 reg = <0 0x942f8000 0 0x8000>; 51 no-map; 52 }; 53 54 dsp_vdev0buffer: memory@94300000 { 55 compatible = "shared-dma-pool"; 56 reg = <0 0x94300000 0 0x100000>; 57 no-map; 58 }; 59 }; 60 61 reg_usdhc2_vmmc: usdhc2-vmmc { 62 compatible = "regulator-fixed"; 63 regulator-name = "SD1_SPWR"; 64 regulator-min-microvolt = <3000000>; 65 regulator-max-microvolt = <3000000>; 66 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 67 enable-active-high; 68 }; 69 70 gpio-sbu-mux { 71 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_typec_mux>; 74 select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; 75 enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>; 76 orientation-switch; 77 78 port { 79 usb3_data_ss: endpoint { 80 remote-endpoint = <&typec_con_ss>; 81 }; 82 }; 83 }; 84 85 reg_pcieb: regulator-pcie { 86 compatible = "regulator-fixed"; 87 regulator-max-microvolt = <3300000>; 88 regulator-min-microvolt = <3300000>; 89 regulator-name = "mpcie_3v3"; 90 gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; 91 enable-active-high; 92 }; 93 94 reg_audio: regulator-audio { 95 compatible = "regulator-fixed"; 96 regulator-max-microvolt = <3300000>; 97 regulator-min-microvolt = <3300000>; 98 regulator-name = "cs42888_supply"; 99 }; 100 101 reg_can_en: regulator-can-en { 102 compatible = "regulator-fixed"; 103 regulator-max-microvolt = <3300000>; 104 regulator-min-microvolt = <3300000>; 105 regulator-name = "can-en"; 106 gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 }; 109 110 reg_can_stby: regulator-can-stby { 111 compatible = "regulator-fixed"; 112 regulator-max-microvolt = <3300000>; 113 regulator-min-microvolt = <3300000>; 114 regulator-name = "can-stby"; 115 gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; 116 enable-active-high; 117 vin-supply = <®_can_en>; 118 }; 119 120 reg_usb_otg1_vbus: regulator-usbotg1-vbus { 121 compatible = "regulator-fixed"; 122 regulator-max-microvolt = <5000000>; 123 regulator-min-microvolt = <5000000>; 124 regulator-name = "usb_otg1_vbus"; 125 gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; 126 enable-active-high; 127 }; 128 129 reserved-memory { 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 vdev0vring0: memory@90000000 { 135 reg = <0 0x90000000 0 0x8000>; 136 no-map; 137 }; 138 139 vdev0vring1: memory@90008000 { 140 reg = <0 0x90008000 0 0x8000>; 141 no-map; 142 }; 143 144 vdev1vring0: memory@90010000 { 145 reg = <0 0x90010000 0 0x8000>; 146 no-map; 147 }; 148 149 vdev1vring1: memory@90018000 { 150 reg = <0 0x90018000 0 0x8000>; 151 no-map; 152 }; 153 154 rsc_table: memory@900ff000 { 155 reg = <0 0x900ff000 0 0x1000>; 156 no-map; 157 }; 158 159 vdevbuffer: memory@90400000 { 160 compatible = "shared-dma-pool"; 161 reg = <0 0x90400000 0 0x100000>; 162 no-map; 163 }; 164 165 gpu_reserved: memory@880000000 { 166 no-map; 167 reg = <0x8 0x80000000 0 0x10000000>; 168 }; 169 }; 170 171 sound-bt-sco { 172 compatible = "simple-audio-card"; 173 simple-audio-card,bitclock-inversion; 174 simple-audio-card,bitclock-master = <&btcpu>; 175 simple-audio-card,format = "dsp_a"; 176 simple-audio-card,frame-master = <&btcpu>; 177 simple-audio-card,name = "bt-sco-audio"; 178 179 simple-audio-card,codec { 180 sound-dai = <&bt_sco_codec 1>; 181 }; 182 183 btcpu: simple-audio-card,cpu { 184 dai-tdm-slot-num = <2>; 185 dai-tdm-slot-width = <16>; 186 sound-dai = <&sai0>; 187 }; 188 }; 189 190 sound-cs42888 { 191 compatible = "fsl,imx-audio-cs42888"; 192 audio-asrc = <&asrc0>; 193 audio-codec = <&cs42888>; 194 audio-cpu = <&esai0>; 195 audio-routing = 196 "Line Out Jack", "AOUT1L", 197 "Line Out Jack", "AOUT1R", 198 "Line Out Jack", "AOUT2L", 199 "Line Out Jack", "AOUT2R", 200 "Line Out Jack", "AOUT3L", 201 "Line Out Jack", "AOUT3R", 202 "Line Out Jack", "AOUT4L", 203 "Line Out Jack", "AOUT4R", 204 "AIN1L", "Line In Jack", 205 "AIN1R", "Line In Jack", 206 "AIN2L", "Line In Jack", 207 "AIN2R", "Line In Jack"; 208 model = "imx-cs42888"; 209 }; 210 211 sound-wm8960 { 212 compatible = "fsl,imx-audio-wm8960"; 213 model = "wm8960-audio"; 214 audio-cpu = <&sai1>; 215 audio-codec = <&wm8960>; 216 hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; 217 audio-routing = "Headphone Jack", "HP_L", 218 "Headphone Jack", "HP_R", 219 "Ext Spk", "SPK_LP", 220 "Ext Spk", "SPK_LN", 221 "Ext Spk", "SPK_RP", 222 "Ext Spk", "SPK_RN", 223 "LINPUT1", "Mic Jack", 224 "Mic Jack", "MICB"; 225 }; 226}; 227 228&amix { 229 status = "okay"; 230}; 231 232&asrc0 { 233 fsl,asrc-rate = <48000>; 234 status = "okay"; 235}; 236 237&dsp { 238 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 239 <&dsp_vdev0vring1>, <&dsp_reserved>; 240 status = "okay"; 241}; 242 243&dsp_reserved { 244 status = "okay"; 245}; 246 247&esai0 { 248 assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, 249 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 250 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 251 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 252 <&esai0_lpcg IMX_LPCG_CLK_0>; 253 assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; 254 assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; 255 pinctrl-0 = <&pinctrl_esai0>; 256 pinctrl-names = "default"; 257 status = "okay"; 258}; 259 260&fec1 { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_fec1>; 263 phy-mode = "rgmii-id"; 264 phy-handle = <ðphy0>; 265 fsl,magic-packet; 266 status = "okay"; 267 268 mdio { 269 #address-cells = <1>; 270 #size-cells = <0>; 271 272 ethphy0: ethernet-phy@0 { 273 compatible = "ethernet-phy-ieee802.3-c22"; 274 reg = <0>; 275 }; 276 }; 277}; 278 279&i2c1 { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 clock-frequency = <100000>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; 285 status = "okay"; 286 287 i2c-mux@71 { 288 compatible = "nxp,pca9646", "nxp,pca9546"; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 reg = <0x71>; 292 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; 293 294 i2c@0 { 295 #address-cells = <1>; 296 #size-cells = <0>; 297 reg = <0>; 298 299 max7322: gpio@68 { 300 compatible = "maxim,max7322"; 301 reg = <0x68>; 302 gpio-controller; 303 #gpio-cells = <2>; 304 }; 305 }; 306 307 i2c@1 { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 reg = <1>; 311 }; 312 313 i2c@2 { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 reg = <2>; 317 318 pressure-sensor@60 { 319 compatible = "fsl,mpl3115"; 320 reg = <0x60>; 321 }; 322 }; 323 324 i2c@3 { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 reg = <3>; 328 329 pca9557_a: gpio@1a { 330 compatible = "nxp,pca9557"; 331 reg = <0x1a>; 332 gpio-controller; 333 #gpio-cells = <2>; 334 }; 335 336 pca9557_b: gpio@1d { 337 compatible = "nxp,pca9557"; 338 reg = <0x1d>; 339 gpio-controller; 340 #gpio-cells = <2>; 341 }; 342 343 light-sensor@44 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_isl29023>; 346 compatible = "isil,isl29023"; 347 reg = <0x44>; 348 interrupt-parent = <&lsio_gpio1>; 349 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 350 }; 351 }; 352 }; 353 354 ptn5110: tcpc@50 { 355 compatible = "nxp,ptn5110", "tcpci"; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_typec>; 358 reg = <0x50>; 359 interrupt-parent = <&lsio_gpio1>; 360 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 361 362 usb_con1: connector { 363 compatible = "usb-c-connector"; 364 label = "USB-C"; 365 power-role = "source"; 366 data-role = "dual"; 367 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 368 369 ports { 370 #address-cells = <1>; 371 #size-cells = <0>; 372 373 port@0 { 374 reg = <0>; 375 376 typec_dr_sw: endpoint { 377 remote-endpoint = <&usb3_drd_sw>; 378 }; 379 }; 380 381 port@1 { 382 reg = <1>; 383 384 typec_con_ss: endpoint { 385 remote-endpoint = <&usb3_data_ss>; 386 }; 387 }; 388 }; 389 }; 390 }; 391 392}; 393 394&cm40_i2c { 395 #address-cells = <1>; 396 #size-cells = <0>; 397 clock-frequency = <100000>; 398 pinctrl-names = "default", "gpio"; 399 pinctrl-0 = <&pinctrl_cm40_i2c>; 400 pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; 401 scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; 402 sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; 403 status = "okay"; 404 405 wm8960: audio-codec@1a { 406 compatible = "wlf,wm8960"; 407 reg = <0x1a>; 408 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 409 clock-names = "mclk"; 410 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 411 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 412 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 413 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 414 assigned-clock-rates = <786432000>, 415 <49152000>, 416 <12288000>, 417 <12288000>; 418 wlf,shared-lrclk; 419 wlf,hp-cfg = <2 2 3>; 420 wlf,gpio-cfg = <1 3>; 421 }; 422 423 pca6416: gpio@20 { 424 compatible = "ti,tca6416"; 425 reg = <0x20>; 426 gpio-controller; 427 #gpio-cells = <2>; 428 }; 429 430 cs42888: audio-codec@48 { 431 compatible = "cirrus,cs42888"; 432 reg = <0x48>; 433 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 434 clock-names = "mclk"; 435 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 436 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 437 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 438 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 439 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 440 reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>; 441 VA-supply = <®_audio>; 442 VD-supply = <®_audio>; 443 VLC-supply = <®_audio>; 444 VLS-supply = <®_audio>; 445 }; 446}; 447 448&cm40_intmux { 449 status = "okay"; 450}; 451 452&hsio_phy { 453 fsl,hsio-cfg = "pciea-x2-pcieb"; 454 fsl,refclk-pad-mode = "input"; 455 status = "okay"; 456}; 457 458&flexcan1 { 459 pinctrl-0 = <&pinctrl_flexcan1>; 460 pinctrl-names = "default"; 461 xceiver-supply = <®_can_stby>; 462 status = "okay"; 463}; 464 465&flexcan2 { 466 pinctrl-0 = <&pinctrl_flexcan2>; 467 pinctrl-names = "default"; 468 xceiver-supply = <®_can_stby>; 469 status = "okay"; 470}; 471 472&jpegdec { 473 status = "okay"; 474}; 475 476&jpegenc { 477 status = "okay"; 478}; 479 480&lpuart0 { 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_lpuart0>; 483 status = "okay"; 484}; 485 486&lpuart2 { 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pinctrl_lpuart2>; 489 status = "okay"; 490}; 491 492&lpuart3 { 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_lpuart3>; 495 status = "okay"; 496}; 497 498&lsio_mu5 { 499 status = "okay"; 500}; 501 502&mu_m0 { 503 status = "okay"; 504}; 505 506&mu1_m0 { 507 status = "okay"; 508}; 509 510&pcieb { 511 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 512 phy-names = "pcie-phy"; 513 pinctrl-0 = <&pinctrl_pcieb>; 514 pinctrl-names = "default"; 515 reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; 516 vpcie-supply = <®_pcieb>; 517 status = "okay"; 518}; 519 520&scu_key { 521 status = "okay"; 522}; 523 524&sai0 { 525 #sound-dai-cells = <0>; 526 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 527 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 528 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 529 <&sai0_lpcg IMX_LPCG_CLK_0>; 530 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 531 pinctrl-names = "default"; 532 pinctrl-0 = <&pinctrl_sai0>; 533 status = "okay"; 534}; 535 536&sai1 { 537 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 538 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 539 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 540 <&sai1_lpcg IMX_LPCG_CLK_0>; 541 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&pinctrl_sai1>; 544 status = "okay"; 545}; 546 547&sai4 { 548 assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, 549 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 550 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 551 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 552 <&sai4_lpcg IMX_LPCG_CLK_0>; 553 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 554 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 555 fsl,sai-asynchronous; 556 status = "okay"; 557}; 558 559&sai5 { 560 assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, 561 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 562 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 563 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 564 <&sai5_lpcg IMX_LPCG_CLK_0>; 565 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 566 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 567 fsl,sai-asynchronous; 568 status = "okay"; 569}; 570 571&thermal_zones { 572 pmic-thermal { 573 polling-delay-passive = <250>; 574 polling-delay = <2000>; 575 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 576 577 trips { 578 pmic_alert0: trip0 { 579 temperature = <110000>; 580 hysteresis = <2000>; 581 type = "passive"; 582 }; 583 584 pmic_crit0: trip1 { 585 temperature = <125000>; 586 hysteresis = <2000>; 587 type = "critical"; 588 }; 589 }; 590 591 cooling-maps { 592 map0 { 593 trip = <&pmic_alert0>; 594 cooling-device = 595 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 596 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 597 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 598 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 599 }; 600 }; 601 }; 602}; 603 604&usdhc1 { 605 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; 606 assigned-clock-rates = <200000000>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&pinctrl_usdhc1>; 609 bus-width = <8>; 610 no-sd; 611 no-sdio; 612 non-removable; 613 status = "okay"; 614}; 615 616&usdhc2 { 617 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; 618 assigned-clock-rates = <200000000>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&pinctrl_usdhc2>; 621 bus-width = <4>; 622 vmmc-supply = <®_usdhc2_vmmc>; 623 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; 624 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; 625 status = "okay"; 626}; 627 628&usb3_phy { 629 status = "okay"; 630}; 631 632&usbphy1 { 633 status = "okay"; 634}; 635 636&usbotg1 { 637 adp-disable; 638 hnp-disable; 639 srp-disable; 640 disable-over-current; 641 power-active-high; 642 vbus-supply = <®_usb_otg1_vbus>; 643 status = "okay"; 644}; 645 646&usbotg3 { 647 status = "okay"; 648}; 649 650&usbotg3_cdns3 { 651 dr_mode = "otg"; 652 usb-role-switch; 653 status = "okay"; 654 655 port { 656 usb3_drd_sw: endpoint { 657 remote-endpoint = <&typec_dr_sw>; 658 }; 659 }; 660}; 661 662 663&vpu { 664 compatible = "nxp,imx8qxp-vpu"; 665 status = "okay"; 666}; 667 668&vpu_core0 { 669 reg = <0x2d040000 0x10000>; 670 memory-region = <&decoder_boot>, <&decoder_rpc>; 671 status = "okay"; 672}; 673 674&vpu_core1 { 675 reg = <0x2d050000 0x10000>; 676 memory-region = <&encoder_boot>, <&encoder_rpc>; 677 status = "okay"; 678}; 679 680&iomuxc { 681 682 pinctrl_cm40_i2c: cm40i2cgrp { 683 fsl,pins = < 684 IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c 685 IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c 686 >; 687 }; 688 689 pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp { 690 fsl,pins = < 691 IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c 692 IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c 693 >; 694 }; 695 696 pinctrl_esai0: esai0grp { 697 fsl,pins = < 698 IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 699 IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 700 IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 701 IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 702 IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 703 IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 704 IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 705 IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 706 IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 707 IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 708 >; 709 }; 710 711 pinctrl_fec1: fec1grp { 712 fsl,pins = < 713 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 714 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 715 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 716 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 717 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 718 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 719 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 720 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 721 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 722 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 723 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 724 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 725 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 726 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 727 >; 728 }; 729 730 pinctrl_flexcan1: flexcan0grp { 731 fsl,pins = < 732 IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 733 IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 734 >; 735 }; 736 737 pinctrl_flexcan2: flexcan1grp { 738 fsl,pins = < 739 IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 740 IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 741 >; 742 }; 743 744 pinctrl_ioexp_rst: ioexprstgrp { 745 fsl,pins = < 746 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 747 >; 748 }; 749 750 pinctrl_isl29023: isl29023grp { 751 fsl,pins = < 752 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 753 >; 754 }; 755 756 pinctrl_lpi2c1: lpi2c1grp { 757 fsl,pins = < 758 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 759 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 760 >; 761 }; 762 763 pinctrl_lpuart0: lpuart0grp { 764 fsl,pins = < 765 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 766 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 767 >; 768 }; 769 770 pinctrl_lpuart2: lpuart2grp { 771 fsl,pins = < 772 IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 773 IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 774 >; 775 }; 776 777 pinctrl_lpuart3: lpuart3grp { 778 fsl,pins = < 779 IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 780 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 781 >; 782 }; 783 784 pinctrl_pcieb: pcieagrp { 785 fsl,pins = < 786 IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 787 IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000021 788 IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 789 >; 790 }; 791 792 pinctrl_typec: typecgrp { 793 fsl,pins = < 794 IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 795 >; 796 }; 797 798 pinctrl_typec_mux: typecmuxgrp { 799 fsl,pins = < 800 IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 801 >; 802 }; 803 804 pinctrl_sai0: sai0grp { 805 fsl,pins = < 806 IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060 807 IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040 808 IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040 809 IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040 810 >; 811 }; 812 813 pinctrl_sai1: sai1grp { 814 fsl,pins = < 815 IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 816 IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 817 IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 818 IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 819 IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 820 >; 821 }; 822 823 pinctrl_usdhc1: usdhc1grp { 824 fsl,pins = < 825 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 826 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 827 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 828 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 829 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 830 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 831 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 832 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 833 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 834 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 835 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 836 >; 837 }; 838 839 pinctrl_usdhc2: usdhc2grp { 840 fsl,pins = < 841 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 842 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 843 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 844 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 845 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 846 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 847 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 848 >; 849 }; 850}; 851