1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017~2018 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8qxp.dtsi" 9#include <dt-bindings/usb/pd.h> 10 11/ { 12 model = "Freescale i.MX8QXP MEK"; 13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 14 15 bt_sco_codec: audio-codec-bt { 16 compatible = "linux,bt-sco"; 17 #sound-dai-cells = <1>; 18 }; 19 20 chosen { 21 stdout-path = &lpuart0; 22 }; 23 24 imx8x_cm4: imx8x-cm4 { 25 compatible = "fsl,imx8qxp-cm4"; 26 mbox-names = "tx", "rx", "rxdb"; 27 mboxes = <&lsio_mu5 0 1 28 &lsio_mu5 1 1 29 &lsio_mu5 3 1>; 30 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 31 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 32 power-domains = <&pd IMX_SC_R_M4_0_PID0>, 33 <&pd IMX_SC_R_M4_0_MU_1A>; 34 fsl,entry-address = <0x34fe0000>; 35 fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 36 }; 37 38 memory@80000000 { 39 device_type = "memory"; 40 reg = <0x00000000 0x80000000 0 0x40000000>; 41 }; 42 43 reg_usdhc2_vmmc: usdhc2-vmmc { 44 compatible = "regulator-fixed"; 45 regulator-name = "SD1_SPWR"; 46 regulator-min-microvolt = <3000000>; 47 regulator-max-microvolt = <3000000>; 48 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 49 enable-active-high; 50 }; 51 52 gpio-sbu-mux { 53 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 54 pinctrl-names = "default"; 55 pinctrl-0 = <&pinctrl_typec_mux>; 56 select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; 57 enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>; 58 orientation-switch; 59 60 port { 61 usb3_data_ss: endpoint { 62 remote-endpoint = <&typec_con_ss>; 63 }; 64 }; 65 }; 66 67 i2c-mux { 68 compatible = "i2c-mux-gpio"; 69 mux-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; /* needs to be an unused GPIO */ 70 i2c-parent = <&cm40_i2c>; 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 i2c@0 { 75 reg = <0>; 76 #address-cells = <1>; 77 #size-cells = <0>; 78 79 wm8960: audio-codec@1a { 80 compatible = "wlf,wm8960"; 81 reg = <0x1a>; 82 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 83 clock-names = "mclk"; 84 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 85 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 86 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 87 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 88 assigned-clock-rates = <786432000>, 89 <49152000>, 90 <12288000>, 91 <12288000>; 92 wlf,shared-lrclk; 93 wlf,hp-cfg = <2 2 3>; 94 wlf,gpio-cfg = <1 3>; 95 AVDD-supply = <®_audio_3v3>; 96 DBVDD-supply = <®_audio_1v8>; 97 DCVDD-supply = <®_audio_1v8>; 98 SPKVDD1-supply = <®_audio_5v>; 99 SPKVDD2-supply = <®_audio_5v>; 100 }; 101 }; 102 103 i2c@1 { 104 reg = <1>; 105 #address-cells = <1>; 106 #size-cells = <0>; 107 108 wm8962: wm8962@1a { 109 compatible = "wlf,wm8962"; 110 reg = <0x1a>; 111 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 112 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 113 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 114 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 115 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 116 assigned-clock-rates = <786432000>, 117 <49152000>, 118 <12288000>, 119 <12288000>; 120 DCVDD-supply = <®_audio_1v8>; 121 DBVDD-supply = <®_audio_1v8>; 122 AVDD-supply = <®_audio_1v8>; 123 CPVDD-supply = <®_audio_1v8>; 124 MICVDD-supply = <®_audio_3v3>; 125 PLLVDD-supply = <®_audio_1v8>; 126 SPKVDD1-supply = <®_audio_5v>; 127 SPKVDD2-supply = <®_audio_5v>; 128 }; 129 }; 130 }; 131 132 reg_1v5: regulator-1v5 { 133 compatible = "regulator-fixed"; 134 regulator-name = "1v5"; 135 regulator-min-microvolt = <1500000>; 136 regulator-max-microvolt = <1500000>; 137 }; 138 139 reg_1v8: regulator-1v8 { 140 compatible = "regulator-fixed"; 141 regulator-name = "1v8"; 142 regulator-min-microvolt = <1800000>; 143 regulator-max-microvolt = <1800000>; 144 }; 145 146 reg_2v8: regulator-2v8 { 147 compatible = "regulator-fixed"; 148 regulator-name = "2v8"; 149 regulator-min-microvolt = <2800000>; 150 regulator-max-microvolt = <2800000>; 151 }; 152 153 reg_pcieb: regulator-pcie { 154 compatible = "regulator-fixed"; 155 regulator-max-microvolt = <3300000>; 156 regulator-min-microvolt = <3300000>; 157 regulator-name = "mpcie_3v3"; 158 gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; 159 enable-active-high; 160 }; 161 162 reg_audio: regulator-audio { 163 compatible = "regulator-fixed"; 164 regulator-max-microvolt = <3300000>; 165 regulator-min-microvolt = <3300000>; 166 regulator-name = "cs42888_supply"; 167 }; 168 169 reg_audio_5v: regulator-audio-pwr { 170 compatible = "regulator-fixed"; 171 regulator-name = "audio-5v"; 172 regulator-min-microvolt = <5000000>; 173 regulator-max-microvolt = <5000000>; 174 regulator-always-on; 175 regulator-boot-on; 176 }; 177 178 reg_audio_3v3: regulator-audio-3v3 { 179 compatible = "regulator-fixed"; 180 regulator-name = "audio-3v3"; 181 regulator-min-microvolt = <3300000>; 182 regulator-max-microvolt = <3300000>; 183 regulator-always-on; 184 regulator-boot-on; 185 }; 186 187 reg_audio_1v8: regulator-audio-1v8 { 188 compatible = "regulator-fixed"; 189 regulator-name = "audio-1v8"; 190 regulator-min-microvolt = <1800000>; 191 regulator-max-microvolt = <1800000>; 192 regulator-always-on; 193 regulator-boot-on; 194 }; 195 196 reg_can_en: regulator-can-en { 197 compatible = "regulator-fixed"; 198 regulator-max-microvolt = <3300000>; 199 regulator-min-microvolt = <3300000>; 200 regulator-name = "can-en"; 201 gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; 202 enable-active-high; 203 }; 204 205 reg_can_stby: regulator-can-stby { 206 compatible = "regulator-fixed"; 207 regulator-max-microvolt = <3300000>; 208 regulator-min-microvolt = <3300000>; 209 regulator-name = "can-stby"; 210 gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; 211 enable-active-high; 212 vin-supply = <®_can_en>; 213 }; 214 215 reg_usb_otg1_vbus: regulator-usbotg1-vbus { 216 compatible = "regulator-fixed"; 217 regulator-max-microvolt = <5000000>; 218 regulator-min-microvolt = <5000000>; 219 regulator-name = "usb_otg1_vbus"; 220 gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; 221 enable-active-high; 222 }; 223 224 reserved-memory { 225 #address-cells = <2>; 226 #size-cells = <2>; 227 ranges; 228 229 vdev0vring0: memory@90000000 { 230 reg = <0 0x90000000 0 0x8000>; 231 no-map; 232 }; 233 234 vdev0vring1: memory@90008000 { 235 reg = <0 0x90008000 0 0x8000>; 236 no-map; 237 }; 238 239 vdev1vring0: memory@90010000 { 240 reg = <0 0x90010000 0 0x8000>; 241 no-map; 242 }; 243 244 vdev1vring1: memory@90018000 { 245 reg = <0 0x90018000 0 0x8000>; 246 no-map; 247 }; 248 249 rsc_table: memory@900ff000 { 250 reg = <0 0x900ff000 0 0x1000>; 251 no-map; 252 }; 253 254 vdevbuffer: memory@90400000 { 255 compatible = "shared-dma-pool"; 256 reg = <0 0x90400000 0 0x100000>; 257 no-map; 258 }; 259 260 dsp_vdev0vring0: memory@942f0000 { 261 reg = <0 0x942f0000 0 0x8000>; 262 no-map; 263 }; 264 265 dsp_vdev0vring1: memory@942f8000 { 266 reg = <0 0x942f8000 0 0x8000>; 267 no-map; 268 }; 269 270 dsp_vdev0buffer: memory@94300000 { 271 compatible = "shared-dma-pool"; 272 reg = <0 0x94300000 0 0x100000>; 273 no-map; 274 }; 275 276 /* global autoconfigured region for contiguous allocations */ 277 linux,cma { 278 compatible = "shared-dma-pool"; 279 alloc-ranges = <0 0xc0000000 0 0x3c000000>; 280 size = <0 0x3c000000>; 281 linux,cma-default; 282 reusable; 283 }; 284 285 gpu_reserved: memory@880000000 { 286 no-map; 287 reg = <0x8 0x80000000 0 0x10000000>; 288 }; 289 }; 290 291 sound-bt-sco { 292 compatible = "simple-audio-card"; 293 simple-audio-card,bitclock-inversion; 294 simple-audio-card,bitclock-master = <&btcpu>; 295 simple-audio-card,format = "dsp_a"; 296 simple-audio-card,frame-master = <&btcpu>; 297 simple-audio-card,name = "bt-sco-audio"; 298 299 simple-audio-card,codec { 300 sound-dai = <&bt_sco_codec 1>; 301 }; 302 303 btcpu: simple-audio-card,cpu { 304 dai-tdm-slot-num = <2>; 305 dai-tdm-slot-width = <16>; 306 sound-dai = <&sai0>; 307 }; 308 }; 309 310 sound-cs42888 { 311 compatible = "fsl,imx-audio-cs42888"; 312 audio-asrc = <&asrc0>; 313 audio-codec = <&cs42888>; 314 audio-cpu = <&esai0>; 315 audio-routing = 316 "Line Out Jack", "AOUT1L", 317 "Line Out Jack", "AOUT1R", 318 "Line Out Jack", "AOUT2L", 319 "Line Out Jack", "AOUT2R", 320 "Line Out Jack", "AOUT3L", 321 "Line Out Jack", "AOUT3R", 322 "Line Out Jack", "AOUT4L", 323 "Line Out Jack", "AOUT4R", 324 "AIN1L", "Line In Jack", 325 "AIN1R", "Line In Jack", 326 "AIN2L", "Line In Jack", 327 "AIN2R", "Line In Jack"; 328 model = "imx-cs42888"; 329 }; 330 331 sound-wm8960 { 332 compatible = "fsl,imx-audio-wm8960"; 333 model = "wm8960-audio"; 334 audio-cpu = <&sai1>; 335 audio-codec = <&wm8960>; 336 hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; 337 audio-routing = "Headphone Jack", "HP_L", 338 "Headphone Jack", "HP_R", 339 "Ext Spk", "SPK_LP", 340 "Ext Spk", "SPK_LN", 341 "Ext Spk", "SPK_RP", 342 "Ext Spk", "SPK_RN", 343 "LINPUT1", "Mic Jack", 344 "Mic Jack", "MICB"; 345 }; 346 347 sound-wm8962 { 348 compatible = "fsl,imx-audio-wm8962"; 349 model = "wm8962-audio"; 350 audio-cpu = <&sai1>; 351 audio-codec = <&wm8962>; 352 hp-det-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; 353 audio-routing = "Headphone Jack", "HPOUTL", 354 "Headphone Jack", "HPOUTR", 355 "Ext Spk", "SPKOUTL", 356 "Ext Spk", "SPKOUTR", 357 "AMIC", "MICBIAS", 358 "IN3R", "AMIC", 359 "IN1R", "AMIC"; 360 }; 361}; 362 363&amix { 364 status = "okay"; 365}; 366 367&asrc0 { 368 fsl,asrc-rate = <48000>; 369 status = "okay"; 370}; 371 372&dsp { 373 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 374 <&dsp_vdev0vring1>, <&dsp_reserved>; 375 status = "okay"; 376}; 377 378&dsp_reserved { 379 status = "okay"; 380}; 381 382&esai0 { 383 assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, 384 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 385 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 386 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 387 <&esai0_lpcg IMX_LPCG_CLK_0>; 388 assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; 389 assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; 390 pinctrl-0 = <&pinctrl_esai0>; 391 pinctrl-names = "default"; 392 status = "okay"; 393}; 394 395&fec1 { 396 pinctrl-names = "default"; 397 pinctrl-0 = <&pinctrl_fec1>; 398 phy-mode = "rgmii-id"; 399 phy-handle = <ðphy0>; 400 fsl,magic-packet; 401 status = "okay"; 402 403 mdio { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 407 ethphy0: ethernet-phy@0 { 408 compatible = "ethernet-phy-ieee802.3-c22"; 409 reg = <0>; 410 }; 411 }; 412}; 413 414&i2c1 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 clock-frequency = <100000>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; 420 status = "okay"; 421 422 i2c-mux@71 { 423 compatible = "nxp,pca9646", "nxp,pca9546"; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 reg = <0x71>; 427 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; 428 429 i2c@0 { 430 #address-cells = <1>; 431 #size-cells = <0>; 432 reg = <0>; 433 434 max7322: gpio@68 { 435 compatible = "maxim,max7322"; 436 reg = <0x68>; 437 gpio-controller; 438 #gpio-cells = <2>; 439 }; 440 }; 441 442 i2c@1 { 443 #address-cells = <1>; 444 #size-cells = <0>; 445 reg = <1>; 446 }; 447 448 i2c@2 { 449 #address-cells = <1>; 450 #size-cells = <0>; 451 reg = <2>; 452 453 pressure-sensor@60 { 454 compatible = "fsl,mpl3115"; 455 reg = <0x60>; 456 }; 457 }; 458 459 i2c@3 { 460 #address-cells = <1>; 461 #size-cells = <0>; 462 reg = <3>; 463 464 pca9557_a: gpio@1a { 465 compatible = "nxp,pca9557"; 466 reg = <0x1a>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 }; 470 471 pca9557_b: gpio@1d { 472 compatible = "nxp,pca9557"; 473 reg = <0x1d>; 474 gpio-controller; 475 #gpio-cells = <2>; 476 }; 477 478 light-sensor@44 { 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pinctrl_isl29023>; 481 compatible = "isil,isl29023"; 482 reg = <0x44>; 483 interrupt-parent = <&lsio_gpio1>; 484 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 485 }; 486 }; 487 }; 488 489 ptn5110: tcpc@50 { 490 compatible = "nxp,ptn5110", "tcpci"; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&pinctrl_typec>; 493 reg = <0x50>; 494 interrupt-parent = <&lsio_gpio1>; 495 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 496 497 usb_con1: connector { 498 compatible = "usb-c-connector"; 499 label = "USB-C"; 500 power-role = "source"; 501 data-role = "dual"; 502 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 503 504 ports { 505 #address-cells = <1>; 506 #size-cells = <0>; 507 508 port@0 { 509 reg = <0>; 510 511 typec_dr_sw: endpoint { 512 remote-endpoint = <&usb3_drd_sw>; 513 }; 514 }; 515 516 port@1 { 517 reg = <1>; 518 519 typec_con_ss: endpoint { 520 remote-endpoint = <&usb3_data_ss>; 521 }; 522 }; 523 }; 524 }; 525 }; 526 527}; 528 529&cm40_i2c { 530 #address-cells = <1>; 531 #size-cells = <0>; 532 clock-frequency = <100000>; 533 pinctrl-names = "default", "gpio"; 534 pinctrl-0 = <&pinctrl_cm40_i2c>; 535 pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; 536 scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; 537 sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; 538 status = "okay"; 539 540 pca6416: gpio@20 { 541 compatible = "ti,tca6416"; 542 reg = <0x20>; 543 gpio-controller; 544 #gpio-cells = <2>; 545 }; 546 547 cs42888: audio-codec@48 { 548 compatible = "cirrus,cs42888"; 549 reg = <0x48>; 550 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 551 clock-names = "mclk"; 552 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 553 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 554 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 555 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 556 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 557 reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>; 558 VA-supply = <®_audio>; 559 VD-supply = <®_audio>; 560 VLC-supply = <®_audio>; 561 VLS-supply = <®_audio>; 562 }; 563}; 564 565&cm40_intmux { 566 status = "okay"; 567}; 568 569&hsio_phy { 570 fsl,hsio-cfg = "pciea-x2-pcieb"; 571 fsl,refclk-pad-mode = "input"; 572 status = "okay"; 573}; 574 575&flexcan1 { 576 pinctrl-0 = <&pinctrl_flexcan1>; 577 pinctrl-names = "default"; 578 xceiver-supply = <®_can_stby>; 579 status = "okay"; 580}; 581 582&flexcan2 { 583 pinctrl-0 = <&pinctrl_flexcan2>; 584 pinctrl-names = "default"; 585 xceiver-supply = <®_can_stby>; 586 status = "okay"; 587}; 588 589&jpegdec { 590 status = "okay"; 591}; 592 593&jpegenc { 594 status = "okay"; 595}; 596 597&lpuart0 { 598 pinctrl-names = "default"; 599 pinctrl-0 = <&pinctrl_lpuart0>; 600 status = "okay"; 601}; 602 603&lpuart2 { 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_lpuart2>; 606 status = "okay"; 607}; 608 609&lpuart3 { 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pinctrl_lpuart3>; 612 status = "okay"; 613}; 614 615&lsio_mu5 { 616 status = "okay"; 617}; 618 619&mu_m0 { 620 status = "okay"; 621}; 622 623&mu1_m0 { 624 status = "okay"; 625}; 626 627&pcie0 { 628 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 629 phy-names = "pcie-phy"; 630 pinctrl-0 = <&pinctrl_pcieb>; 631 pinctrl-names = "default"; 632 reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; 633 vpcie-supply = <®_pcieb>; 634 status = "okay"; 635}; 636 637&pcie0_ep { 638 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 639 phy-names = "pcie-phy"; 640 pinctrl-0 = <&pinctrl_pcieb>; 641 pinctrl-names = "default"; 642 vpcie-supply = <®_pcieb>; 643 status = "disabled"; 644}; 645 646&scu_key { 647 status = "okay"; 648}; 649 650&sai0 { 651 #sound-dai-cells = <0>; 652 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 653 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 654 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 655 <&sai0_lpcg IMX_LPCG_CLK_0>; 656 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&pinctrl_sai0>; 659 status = "okay"; 660}; 661 662&sai1 { 663 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 664 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 665 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 666 <&sai1_lpcg IMX_LPCG_CLK_0>; 667 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_sai1>; 670 status = "okay"; 671}; 672 673&sai4 { 674 assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, 675 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 676 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 677 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 678 <&sai4_lpcg IMX_LPCG_CLK_0>; 679 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 680 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 681 fsl,sai-asynchronous; 682 status = "okay"; 683}; 684 685&sai5 { 686 assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, 687 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 688 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 689 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 690 <&sai5_lpcg IMX_LPCG_CLK_0>; 691 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 692 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 693 fsl,sai-asynchronous; 694 status = "okay"; 695}; 696 697&thermal_zones { 698 pmic-thermal { 699 polling-delay-passive = <250>; 700 polling-delay = <2000>; 701 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 702 703 trips { 704 pmic_alert0: trip0 { 705 temperature = <110000>; 706 hysteresis = <2000>; 707 type = "passive"; 708 }; 709 710 pmic_crit0: trip1 { 711 temperature = <125000>; 712 hysteresis = <2000>; 713 type = "critical"; 714 }; 715 }; 716 717 cooling-maps { 718 map0 { 719 trip = <&pmic_alert0>; 720 cooling-device = 721 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 722 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 723 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 724 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 725 }; 726 }; 727 }; 728}; 729 730&usdhc1 { 731 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; 732 assigned-clock-rates = <200000000>; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&pinctrl_usdhc1>; 735 bus-width = <8>; 736 no-sd; 737 no-sdio; 738 non-removable; 739 status = "okay"; 740}; 741 742&usdhc2 { 743 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; 744 assigned-clock-rates = <200000000>; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&pinctrl_usdhc2>; 747 bus-width = <4>; 748 vmmc-supply = <®_usdhc2_vmmc>; 749 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; 750 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; 751 status = "okay"; 752}; 753 754&usb3_phy { 755 status = "okay"; 756}; 757 758&usbphy1 { 759 status = "okay"; 760}; 761 762&usbotg1 { 763 adp-disable; 764 hnp-disable; 765 srp-disable; 766 disable-over-current; 767 power-active-high; 768 vbus-supply = <®_usb_otg1_vbus>; 769 status = "okay"; 770}; 771 772&usbotg3 { 773 status = "okay"; 774}; 775 776&usbotg3_cdns3 { 777 dr_mode = "otg"; 778 usb-role-switch; 779 status = "okay"; 780 781 port { 782 usb3_drd_sw: endpoint { 783 remote-endpoint = <&typec_dr_sw>; 784 }; 785 }; 786}; 787 788 789&vpu { 790 compatible = "nxp,imx8qxp-vpu"; 791 status = "okay"; 792}; 793 794&vpu_core0 { 795 reg = <0x2d040000 0x10000>; 796 memory-region = <&decoder_boot>, <&decoder_rpc>; 797 status = "okay"; 798}; 799 800&vpu_core1 { 801 reg = <0x2d050000 0x10000>; 802 memory-region = <&encoder_boot>, <&encoder_rpc>; 803 status = "okay"; 804}; 805 806&iomuxc { 807 808 pinctrl_cm40_i2c: cm40i2cgrp { 809 fsl,pins = < 810 IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c 811 IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c 812 >; 813 }; 814 815 pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp { 816 fsl,pins = < 817 IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c 818 IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c 819 >; 820 }; 821 822 pinctrl_esai0: esai0grp { 823 fsl,pins = < 824 IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 825 IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 826 IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 827 IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 828 IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 829 IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 830 IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 831 IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 832 IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 833 IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 834 >; 835 }; 836 837 pinctrl_fec1: fec1grp { 838 fsl,pins = < 839 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 840 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 841 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 842 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 843 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 844 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 845 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 846 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 847 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 848 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 849 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 850 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 851 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 852 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 853 >; 854 }; 855 856 pinctrl_flexcan1: flexcan0grp { 857 fsl,pins = < 858 IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 859 IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 860 >; 861 }; 862 863 pinctrl_flexcan2: flexcan1grp { 864 fsl,pins = < 865 IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 866 IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 867 >; 868 }; 869 870 pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp { 871 fsl,pins = < 872 IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 873 IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 874 >; 875 }; 876 877 pinctrl_ioexp_rst: ioexprstgrp { 878 fsl,pins = < 879 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 880 >; 881 }; 882 883 pinctrl_isl29023: isl29023grp { 884 fsl,pins = < 885 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 886 >; 887 }; 888 889 pinctrl_lpi2c1: lpi2c1grp { 890 fsl,pins = < 891 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 892 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 893 >; 894 }; 895 896 pinctrl_lpuart0: lpuart0grp { 897 fsl,pins = < 898 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 899 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 900 >; 901 }; 902 903 pinctrl_lpuart2: lpuart2grp { 904 fsl,pins = < 905 IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 906 IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 907 >; 908 }; 909 910 pinctrl_lpuart3: lpuart3grp { 911 fsl,pins = < 912 IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 913 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 914 >; 915 }; 916 917 pinctrl_mipi_csi0: mipi-csi0grp { 918 fsl,pins = < 919 IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 920 IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 921 IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 922 >; 923 }; 924 925 pinctrl_pcieb: pcieagrp { 926 fsl,pins = < 927 IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 928 IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000021 929 IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 930 >; 931 }; 932 933 pinctrl_typec: typecgrp { 934 fsl,pins = < 935 IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 936 >; 937 }; 938 939 pinctrl_typec_mux: typecmuxgrp { 940 fsl,pins = < 941 IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 942 >; 943 }; 944 945 pinctrl_sai0: sai0grp { 946 fsl,pins = < 947 IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060 948 IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040 949 IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040 950 IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040 951 >; 952 }; 953 954 pinctrl_sai1: sai1grp { 955 fsl,pins = < 956 IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 957 IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 958 IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 959 IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 960 IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 961 >; 962 }; 963 964 pinctrl_usdhc1: usdhc1grp { 965 fsl,pins = < 966 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 967 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 968 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 969 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 970 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 971 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 972 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 973 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 974 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 975 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 976 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 977 >; 978 }; 979 980 pinctrl_usdhc2: usdhc2grp { 981 fsl,pins = < 982 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 983 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 984 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 985 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 986 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 987 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 988 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 989 >; 990 }; 991}; 992