xref: /linux/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts (revision 8a922b7728a93d837954315c98b84f6b78de0c4f) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017~2018 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8qxp.dtsi"
9
10/ {
11	model = "Freescale i.MX8QXP MEK";
12	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
13
14	chosen {
15		stdout-path = &lpuart0;
16	};
17
18	memory@80000000 {
19		device_type = "memory";
20		reg = <0x00000000 0x80000000 0 0x40000000>;
21	};
22
23	reg_usdhc2_vmmc: usdhc2-vmmc {
24		compatible = "regulator-fixed";
25		regulator-name = "SD1_SPWR";
26		regulator-min-microvolt = <3000000>;
27		regulator-max-microvolt = <3000000>;
28		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
29		enable-active-high;
30	};
31};
32
33&dsp {
34	status = "okay";
35};
36
37&fec1 {
38	pinctrl-names = "default";
39	pinctrl-0 = <&pinctrl_fec1>;
40	phy-mode = "rgmii-id";
41	phy-handle = <&ethphy0>;
42	fsl,magic-packet;
43	status = "okay";
44
45	mdio {
46		#address-cells = <1>;
47		#size-cells = <0>;
48
49		ethphy0: ethernet-phy@0 {
50			compatible = "ethernet-phy-ieee802.3-c22";
51			reg = <0>;
52		};
53	};
54};
55
56&i2c1 {
57	#address-cells = <1>;
58	#size-cells = <0>;
59	clock-frequency = <100000>;
60	pinctrl-names = "default";
61	pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
62	status = "okay";
63
64	i2c-mux@71 {
65		compatible = "nxp,pca9646", "nxp,pca9546";
66		#address-cells = <1>;
67		#size-cells = <0>;
68		reg = <0x71>;
69		reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
70
71		i2c@0 {
72			#address-cells = <1>;
73			#size-cells = <0>;
74			reg = <0>;
75
76			max7322: gpio@68 {
77				compatible = "maxim,max7322";
78				reg = <0x68>;
79				gpio-controller;
80				#gpio-cells = <2>;
81			};
82		};
83
84		i2c@1 {
85			#address-cells = <1>;
86			#size-cells = <0>;
87			reg = <1>;
88		};
89
90		i2c@2 {
91			#address-cells = <1>;
92			#size-cells = <0>;
93			reg = <2>;
94
95			pressure-sensor@60 {
96				compatible = "fsl,mpl3115";
97				reg = <0x60>;
98			};
99		};
100
101		i2c@3 {
102			#address-cells = <1>;
103			#size-cells = <0>;
104			reg = <3>;
105
106			pca9557_a: gpio@1a {
107				compatible = "nxp,pca9557";
108				reg = <0x1a>;
109				gpio-controller;
110				#gpio-cells = <2>;
111			};
112
113			pca9557_b: gpio@1d {
114				compatible = "nxp,pca9557";
115				reg = <0x1d>;
116				gpio-controller;
117				#gpio-cells = <2>;
118			};
119
120			light-sensor@44 {
121				pinctrl-names = "default";
122				pinctrl-0 = <&pinctrl_isl29023>;
123				compatible = "isil,isl29023";
124				reg = <0x44>;
125				interrupt-parent = <&lsio_gpio1>;
126				interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
127			};
128		};
129	};
130};
131
132&lpuart0 {
133	pinctrl-names = "default";
134	pinctrl-0 = <&pinctrl_lpuart0>;
135	status = "okay";
136};
137
138&mu_m0 {
139	status = "okay";
140};
141
142&mu1_m0 {
143	status = "okay";
144};
145
146&scu_key {
147	status = "okay";
148};
149
150&thermal_zones {
151	pmic-thermal0 {
152		polling-delay-passive = <250>;
153		polling-delay = <2000>;
154		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
155
156		trips {
157			pmic_alert0: trip0 {
158				temperature = <110000>;
159				hysteresis = <2000>;
160				type = "passive";
161			};
162
163			pmic_crit0: trip1 {
164				temperature = <125000>;
165				hysteresis = <2000>;
166				type = "critical";
167			};
168		};
169
170		cooling-maps {
171			map0 {
172				trip = <&pmic_alert0>;
173				cooling-device =
174					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
175					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
176					<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
177					<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
178			};
179		};
180	};
181};
182
183&usdhc1 {
184	assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
185	assigned-clock-rates = <200000000>;
186	pinctrl-names = "default";
187	pinctrl-0 = <&pinctrl_usdhc1>;
188	bus-width = <8>;
189	no-sd;
190	no-sdio;
191	non-removable;
192	status = "okay";
193};
194
195&usdhc2 {
196	assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
197	assigned-clock-rates = <200000000>;
198	pinctrl-names = "default";
199	pinctrl-0 = <&pinctrl_usdhc2>;
200	bus-width = <4>;
201	vmmc-supply = <&reg_usdhc2_vmmc>;
202	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
203	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
204	status = "okay";
205};
206
207&vpu {
208	compatible = "nxp,imx8qxp-vpu";
209	status = "okay";
210};
211
212&vpu_core0 {
213	reg = <0x2d040000 0x10000>;
214	memory-region = <&decoder_boot>, <&decoder_rpc>;
215	status = "okay";
216};
217
218&vpu_core1 {
219	reg = <0x2d050000 0x10000>;
220	memory-region = <&encoder_boot>, <&encoder_rpc>;
221	status = "okay";
222};
223
224&iomuxc {
225	pinctrl_fec1: fec1grp {
226		fsl,pins = <
227			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
228			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
229			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
230			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
231			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
232			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
233			IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
234			IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
235			IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
236			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
237			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
238			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
239			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
240			IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
241		>;
242	};
243
244	pinctrl_ioexp_rst: ioexprstgrp {
245		fsl,pins = <
246			IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01			0x06000021
247		>;
248	};
249
250	pinctrl_isl29023: isl29023grp {
251		fsl,pins = <
252			IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02			0x00000021
253		>;
254	};
255
256	pinctrl_lpi2c1: lpi2c1grp {
257		fsl,pins = <
258			IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL			0x06000021
259			IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA			0x06000021
260		>;
261	};
262
263	pinctrl_lpuart0: lpuart0grp {
264		fsl,pins = <
265			IMX8QXP_UART0_RX_ADMA_UART0_RX				0x06000020
266			IMX8QXP_UART0_TX_ADMA_UART0_TX				0x06000020
267		>;
268	};
269
270	pinctrl_usdhc1: usdhc1grp {
271		fsl,pins = <
272			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
273			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
274			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
275			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
276			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
277			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
278			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
279			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
280			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
281			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
282			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
283		>;
284	};
285
286	pinctrl_usdhc2: usdhc2grp {
287		fsl,pins = <
288			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
289			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
290			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
291			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
292			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
293			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
294			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
295		>;
296	};
297};
298