1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017~2018 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8qxp.dtsi" 9#include <dt-bindings/usb/pd.h> 10 11/ { 12 model = "Freescale i.MX8QXP MEK"; 13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 14 15 chosen { 16 stdout-path = &lpuart0; 17 }; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x00000000 0x80000000 0 0x40000000>; 22 }; 23 24 reg_usdhc2_vmmc: usdhc2-vmmc { 25 compatible = "regulator-fixed"; 26 regulator-name = "SD1_SPWR"; 27 regulator-min-microvolt = <3000000>; 28 regulator-max-microvolt = <3000000>; 29 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 }; 32 33 gpio-sbu-mux { 34 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_typec_mux>; 37 select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; 38 enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>; 39 orientation-switch; 40 41 port { 42 usb3_data_ss: endpoint { 43 remote-endpoint = <&typec_con_ss>; 44 }; 45 }; 46 }; 47 48 sound-wm8960 { 49 compatible = "fsl,imx-audio-wm8960"; 50 model = "wm8960-audio"; 51 audio-cpu = <&sai1>; 52 audio-codec = <&wm8960>; 53 hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; 54 audio-routing = "Headphone Jack", "HP_L", 55 "Headphone Jack", "HP_R", 56 "Ext Spk", "SPK_LP", 57 "Ext Spk", "SPK_LN", 58 "Ext Spk", "SPK_RP", 59 "Ext Spk", "SPK_RN", 60 "LINPUT1", "Mic Jack", 61 "Mic Jack", "MICB"; 62 }; 63}; 64 65&dsp { 66 memory-region = <&dsp_reserved>; 67 status = "okay"; 68}; 69 70&dsp_reserved { 71 status = "okay"; 72}; 73 74&fec1 { 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_fec1>; 77 phy-mode = "rgmii-id"; 78 phy-handle = <ðphy0>; 79 fsl,magic-packet; 80 status = "okay"; 81 82 mdio { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 ethphy0: ethernet-phy@0 { 87 compatible = "ethernet-phy-ieee802.3-c22"; 88 reg = <0>; 89 }; 90 }; 91}; 92 93&i2c1 { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 clock-frequency = <100000>; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; 99 status = "okay"; 100 101 i2c-mux@71 { 102 compatible = "nxp,pca9646", "nxp,pca9546"; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 reg = <0x71>; 106 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; 107 108 i2c@0 { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 reg = <0>; 112 113 max7322: gpio@68 { 114 compatible = "maxim,max7322"; 115 reg = <0x68>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 }; 119 }; 120 121 i2c@1 { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 reg = <1>; 125 }; 126 127 i2c@2 { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 reg = <2>; 131 132 pressure-sensor@60 { 133 compatible = "fsl,mpl3115"; 134 reg = <0x60>; 135 }; 136 }; 137 138 i2c@3 { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 reg = <3>; 142 143 pca9557_a: gpio@1a { 144 compatible = "nxp,pca9557"; 145 reg = <0x1a>; 146 gpio-controller; 147 #gpio-cells = <2>; 148 }; 149 150 pca9557_b: gpio@1d { 151 compatible = "nxp,pca9557"; 152 reg = <0x1d>; 153 gpio-controller; 154 #gpio-cells = <2>; 155 }; 156 157 light-sensor@44 { 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_isl29023>; 160 compatible = "isil,isl29023"; 161 reg = <0x44>; 162 interrupt-parent = <&lsio_gpio1>; 163 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 164 }; 165 }; 166 }; 167 168 ptn5110: tcpc@50 { 169 compatible = "nxp,ptn5110", "tcpci"; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_typec>; 172 reg = <0x50>; 173 interrupt-parent = <&lsio_gpio1>; 174 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 175 176 usb_con1: connector { 177 compatible = "usb-c-connector"; 178 label = "USB-C"; 179 power-role = "source"; 180 data-role = "dual"; 181 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 182 183 ports { 184 #address-cells = <1>; 185 #size-cells = <0>; 186 187 port@0 { 188 reg = <0>; 189 190 typec_dr_sw: endpoint { 191 remote-endpoint = <&usb3_drd_sw>; 192 }; 193 }; 194 195 port@1 { 196 reg = <1>; 197 198 typec_con_ss: endpoint { 199 remote-endpoint = <&usb3_data_ss>; 200 }; 201 }; 202 }; 203 }; 204 }; 205 206}; 207 208&cm40_i2c { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 clock-frequency = <100000>; 212 pinctrl-names = "default", "gpio"; 213 pinctrl-0 = <&pinctrl_cm40_i2c>; 214 pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; 215 scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; 216 sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; 217 status = "okay"; 218 219 wm8960: audio-codec@1a { 220 compatible = "wlf,wm8960"; 221 reg = <0x1a>; 222 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 223 clock-names = "mclk"; 224 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 225 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 226 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 227 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 228 assigned-clock-rates = <786432000>, 229 <49152000>, 230 <12288000>, 231 <12288000>; 232 wlf,shared-lrclk; 233 wlf,hp-cfg = <2 2 3>; 234 wlf,gpio-cfg = <1 3>; 235 }; 236 237 pca6416: gpio@20 { 238 compatible = "ti,tca6416"; 239 reg = <0x20>; 240 gpio-controller; 241 #gpio-cells = <2>; 242 }; 243}; 244 245&cm40_intmux { 246 status = "okay"; 247}; 248 249&lpuart0 { 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_lpuart0>; 252 status = "okay"; 253}; 254 255&lpuart2 { 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_lpuart2>; 258 status = "okay"; 259}; 260 261&lpuart3 { 262 pinctrl-names = "default"; 263 pinctrl-0 = <&pinctrl_lpuart3>; 264 status = "okay"; 265}; 266 267&mu_m0 { 268 status = "okay"; 269}; 270 271&mu1_m0 { 272 status = "okay"; 273}; 274 275&scu_key { 276 status = "okay"; 277}; 278 279&sai0 { 280 #sound-dai-cells = <0>; 281 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 282 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 283 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 284 <&sai0_lpcg IMX_LPCG_CLK_0>; 285 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_sai0>; 288 status = "okay"; 289}; 290 291&sai1 { 292 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 293 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 294 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 295 <&sai1_lpcg IMX_LPCG_CLK_0>; 296 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_sai1>; 299 status = "okay"; 300}; 301 302&sai4 { 303 assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, 304 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 305 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 306 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 307 <&sai4_lpcg IMX_LPCG_CLK_0>; 308 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 309 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 310 fsl,sai-asynchronous; 311 status = "okay"; 312}; 313 314&sai5 { 315 assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, 316 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 317 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 318 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 319 <&sai5_lpcg IMX_LPCG_CLK_0>; 320 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 321 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 322 fsl,sai-asynchronous; 323 status = "okay"; 324}; 325 326&thermal_zones { 327 pmic-thermal { 328 polling-delay-passive = <250>; 329 polling-delay = <2000>; 330 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 331 332 trips { 333 pmic_alert0: trip0 { 334 temperature = <110000>; 335 hysteresis = <2000>; 336 type = "passive"; 337 }; 338 339 pmic_crit0: trip1 { 340 temperature = <125000>; 341 hysteresis = <2000>; 342 type = "critical"; 343 }; 344 }; 345 346 cooling-maps { 347 map0 { 348 trip = <&pmic_alert0>; 349 cooling-device = 350 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 351 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 352 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 353 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 354 }; 355 }; 356 }; 357}; 358 359&usdhc1 { 360 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; 361 assigned-clock-rates = <200000000>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_usdhc1>; 364 bus-width = <8>; 365 no-sd; 366 no-sdio; 367 non-removable; 368 status = "okay"; 369}; 370 371&usdhc2 { 372 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; 373 assigned-clock-rates = <200000000>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&pinctrl_usdhc2>; 376 bus-width = <4>; 377 vmmc-supply = <®_usdhc2_vmmc>; 378 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; 379 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; 380 status = "okay"; 381}; 382 383&usb3_phy { 384 status = "okay"; 385}; 386 387&usbotg3 { 388 status = "okay"; 389}; 390 391&usbotg3_cdns3 { 392 dr_mode = "otg"; 393 usb-role-switch; 394 status = "okay"; 395 396 port { 397 usb3_drd_sw: endpoint { 398 remote-endpoint = <&typec_dr_sw>; 399 }; 400 }; 401}; 402 403 404&vpu { 405 compatible = "nxp,imx8qxp-vpu"; 406 status = "okay"; 407}; 408 409&vpu_core0 { 410 reg = <0x2d040000 0x10000>; 411 memory-region = <&decoder_boot>, <&decoder_rpc>; 412 status = "okay"; 413}; 414 415&vpu_core1 { 416 reg = <0x2d050000 0x10000>; 417 memory-region = <&encoder_boot>, <&encoder_rpc>; 418 status = "okay"; 419}; 420 421&iomuxc { 422 423 pinctrl_cm40_i2c: cm40i2cgrp { 424 fsl,pins = < 425 IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c 426 IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c 427 >; 428 }; 429 430 pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp { 431 fsl,pins = < 432 IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c 433 IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c 434 >; 435 }; 436 437 pinctrl_fec1: fec1grp { 438 fsl,pins = < 439 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 440 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 441 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 442 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 443 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 444 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 445 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 446 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 447 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 448 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 449 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 450 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 451 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 452 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 453 >; 454 }; 455 456 pinctrl_ioexp_rst: ioexprstgrp { 457 fsl,pins = < 458 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 459 >; 460 }; 461 462 pinctrl_isl29023: isl29023grp { 463 fsl,pins = < 464 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 465 >; 466 }; 467 468 pinctrl_lpi2c1: lpi2c1grp { 469 fsl,pins = < 470 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 471 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 472 >; 473 }; 474 475 pinctrl_lpuart0: lpuart0grp { 476 fsl,pins = < 477 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 478 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 479 >; 480 }; 481 482 pinctrl_lpuart2: lpuart2grp { 483 fsl,pins = < 484 IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 485 IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 486 >; 487 }; 488 489 pinctrl_lpuart3: lpuart3grp { 490 fsl,pins = < 491 IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 492 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 493 >; 494 }; 495 496 pinctrl_typec: typecgrp { 497 fsl,pins = < 498 IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 499 >; 500 }; 501 502 pinctrl_typec_mux: typecmuxgrp { 503 fsl,pins = < 504 IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 505 >; 506 }; 507 508 pinctrl_sai0: sai0grp { 509 fsl,pins = < 510 IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060 511 IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040 512 IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040 513 IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040 514 >; 515 }; 516 517 pinctrl_sai1: sai1grp { 518 fsl,pins = < 519 IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 520 IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 521 IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 522 IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 523 IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 524 >; 525 }; 526 527 pinctrl_usdhc1: usdhc1grp { 528 fsl,pins = < 529 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 530 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 531 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 532 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 533 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 534 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 535 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 536 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 537 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 538 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 539 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 540 >; 541 }; 542 543 pinctrl_usdhc2: usdhc2grp { 544 fsl,pins = < 545 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 546 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 547 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 548 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 549 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 550 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 551 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 552 >; 553 }; 554}; 555