1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017~2018 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8qxp.dtsi" 9 10/ { 11 model = "Freescale i.MX8QXP MEK"; 12 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 13 14 chosen { 15 stdout-path = &adma_lpuart0; 16 }; 17 18 memory@80000000 { 19 device_type = "memory"; 20 reg = <0x00000000 0x80000000 0 0x40000000>; 21 }; 22 23 reg_usdhc2_vmmc: usdhc2-vmmc { 24 compatible = "regulator-fixed"; 25 regulator-name = "SD1_SPWR"; 26 regulator-min-microvolt = <3000000>; 27 regulator-max-microvolt = <3000000>; 28 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 29 enable-active-high; 30 }; 31}; 32 33&adma_dsp { 34 status = "okay"; 35}; 36 37&adma_i2c1 { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 clock-frequency = <100000>; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; 43 status = "okay"; 44 45 i2c-switch@71 { 46 compatible = "nxp,pca9646", "nxp,pca9546"; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 reg = <0x71>; 50 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; 51 52 i2c@0 { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 reg = <0>; 56 57 max7322: gpio@68 { 58 compatible = "maxim,max7322"; 59 reg = <0x68>; 60 gpio-controller; 61 #gpio-cells = <2>; 62 }; 63 }; 64 65 i2c@1 { 66 #address-cells = <1>; 67 #size-cells = <0>; 68 reg = <1>; 69 }; 70 71 i2c@2 { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 reg = <2>; 75 76 pressure-sensor@60 { 77 compatible = "fsl,mpl3115"; 78 reg = <0x60>; 79 }; 80 }; 81 82 i2c@3 { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 reg = <3>; 86 87 pca9557_a: gpio@1a { 88 compatible = "nxp,pca9557"; 89 reg = <0x1a>; 90 gpio-controller; 91 #gpio-cells = <2>; 92 }; 93 94 pca9557_b: gpio@1d { 95 compatible = "nxp,pca9557"; 96 reg = <0x1d>; 97 gpio-controller; 98 #gpio-cells = <2>; 99 }; 100 101 light-sensor@44 { 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_isl29023>; 104 compatible = "isil,isl29023"; 105 reg = <0x44>; 106 interrupt-parent = <&lsio_gpio1>; 107 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 108 }; 109 }; 110 }; 111}; 112 113&adma_lpuart0 { 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_lpuart0>; 116 status = "okay"; 117}; 118 119&fec1 { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_fec1>; 122 phy-mode = "rgmii-id"; 123 phy-handle = <ðphy0>; 124 fsl,magic-packet; 125 status = "okay"; 126 127 mdio { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 ethphy0: ethernet-phy@0 { 132 compatible = "ethernet-phy-ieee802.3-c22"; 133 reg = <0>; 134 }; 135 }; 136}; 137 138&scu_key { 139 status = "okay"; 140}; 141 142&thermal_zones { 143 pmic-thermal0 { 144 polling-delay-passive = <250>; 145 polling-delay = <2000>; 146 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 147 148 trips { 149 pmic_alert0: trip0 { 150 temperature = <110000>; 151 hysteresis = <2000>; 152 type = "passive"; 153 }; 154 155 pmic_crit0: trip1 { 156 temperature = <125000>; 157 hysteresis = <2000>; 158 type = "critical"; 159 }; 160 }; 161 162 cooling-maps { 163 map0 { 164 trip = <&pmic_alert0>; 165 cooling-device = 166 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 167 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 168 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 169 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 170 }; 171 }; 172 }; 173}; 174 175&usdhc1 { 176 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 177 assigned-clock-rates = <200000000>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_usdhc1>; 180 bus-width = <8>; 181 no-sd; 182 no-sdio; 183 non-removable; 184 status = "okay"; 185}; 186 187&usdhc2 { 188 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 189 assigned-clock-rates = <200000000>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_usdhc2>; 192 bus-width = <4>; 193 vmmc-supply = <®_usdhc2_vmmc>; 194 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; 195 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; 196 status = "okay"; 197}; 198 199&iomuxc { 200 pinctrl_fec1: fec1grp { 201 fsl,pins = < 202 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 203 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 204 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 205 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 206 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 207 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 208 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 209 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 210 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 211 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 212 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 213 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 214 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 215 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 216 >; 217 }; 218 219 pinctrl_ioexp_rst: ioexprstgrp { 220 fsl,pins = < 221 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 222 >; 223 }; 224 225 pinctrl_isl29023: isl29023grp { 226 fsl,pins = < 227 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 228 >; 229 }; 230 231 pinctrl_lpi2c1: lpi2c1grp { 232 fsl,pins = < 233 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 234 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 235 >; 236 }; 237 238 pinctrl_lpuart0: lpuart0grp { 239 fsl,pins = < 240 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 241 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 242 >; 243 }; 244 245 pinctrl_usdhc1: usdhc1grp { 246 fsl,pins = < 247 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 248 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 249 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 250 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 251 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 252 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 253 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 254 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 255 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 256 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 257 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 258 >; 259 }; 260 261 pinctrl_usdhc2: usdhc2grp { 262 fsl,pins = < 263 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 264 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 265 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 266 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 267 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 268 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 269 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 270 >; 271 }; 272}; 273