1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017~2018 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8qxp.dtsi" 9#include <dt-bindings/usb/pd.h> 10 11/ { 12 model = "Freescale i.MX8QXP MEK"; 13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 14 15 chosen { 16 stdout-path = &lpuart0; 17 }; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x00000000 0x80000000 0 0x40000000>; 22 }; 23 24 reg_usdhc2_vmmc: usdhc2-vmmc { 25 compatible = "regulator-fixed"; 26 regulator-name = "SD1_SPWR"; 27 regulator-min-microvolt = <3000000>; 28 regulator-max-microvolt = <3000000>; 29 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 }; 32 33 gpio-sbu-mux { 34 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_typec_mux>; 37 select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; 38 enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>; 39 orientation-switch; 40 41 port { 42 usb3_data_ss: endpoint { 43 remote-endpoint = <&typec_con_ss>; 44 }; 45 }; 46 }; 47 48 sound-wm8960 { 49 compatible = "fsl,imx-audio-wm8960"; 50 model = "wm8960-audio"; 51 audio-cpu = <&sai1>; 52 audio-codec = <&wm8960>; 53 hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; 54 audio-routing = "Headphone Jack", "HP_L", 55 "Headphone Jack", "HP_R", 56 "Ext Spk", "SPK_LP", 57 "Ext Spk", "SPK_LN", 58 "Ext Spk", "SPK_RP", 59 "Ext Spk", "SPK_RN", 60 "LINPUT1", "Mic Jack", 61 "Mic Jack", "MICB"; 62 }; 63}; 64 65&dsp { 66 status = "okay"; 67}; 68 69&dsp_reserved { 70 status = "okay"; 71}; 72 73&fec1 { 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_fec1>; 76 phy-mode = "rgmii-id"; 77 phy-handle = <ðphy0>; 78 fsl,magic-packet; 79 status = "okay"; 80 81 mdio { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 ethphy0: ethernet-phy@0 { 86 compatible = "ethernet-phy-ieee802.3-c22"; 87 reg = <0>; 88 }; 89 }; 90}; 91 92&i2c1 { 93 #address-cells = <1>; 94 #size-cells = <0>; 95 clock-frequency = <100000>; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; 98 status = "okay"; 99 100 i2c-mux@71 { 101 compatible = "nxp,pca9646", "nxp,pca9546"; 102 #address-cells = <1>; 103 #size-cells = <0>; 104 reg = <0x71>; 105 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; 106 107 i2c@0 { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 reg = <0>; 111 112 max7322: gpio@68 { 113 compatible = "maxim,max7322"; 114 reg = <0x68>; 115 gpio-controller; 116 #gpio-cells = <2>; 117 }; 118 }; 119 120 i2c@1 { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 reg = <1>; 124 }; 125 126 i2c@2 { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 reg = <2>; 130 131 pressure-sensor@60 { 132 compatible = "fsl,mpl3115"; 133 reg = <0x60>; 134 }; 135 }; 136 137 i2c@3 { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 reg = <3>; 141 142 pca9557_a: gpio@1a { 143 compatible = "nxp,pca9557"; 144 reg = <0x1a>; 145 gpio-controller; 146 #gpio-cells = <2>; 147 }; 148 149 pca9557_b: gpio@1d { 150 compatible = "nxp,pca9557"; 151 reg = <0x1d>; 152 gpio-controller; 153 #gpio-cells = <2>; 154 }; 155 156 light-sensor@44 { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_isl29023>; 159 compatible = "isil,isl29023"; 160 reg = <0x44>; 161 interrupt-parent = <&lsio_gpio1>; 162 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 163 }; 164 }; 165 }; 166 167 ptn5110: tcpc@50 { 168 compatible = "nxp,ptn5110", "tcpci"; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_typec>; 171 reg = <0x50>; 172 interrupt-parent = <&lsio_gpio1>; 173 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 174 175 usb_con1: connector { 176 compatible = "usb-c-connector"; 177 label = "USB-C"; 178 power-role = "source"; 179 data-role = "dual"; 180 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 181 182 ports { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 port@0 { 187 reg = <0>; 188 189 typec_dr_sw: endpoint { 190 remote-endpoint = <&usb3_drd_sw>; 191 }; 192 }; 193 194 port@1 { 195 reg = <1>; 196 197 typec_con_ss: endpoint { 198 remote-endpoint = <&usb3_data_ss>; 199 }; 200 }; 201 }; 202 }; 203 }; 204 205}; 206 207&cm40_i2c { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 clock-frequency = <100000>; 211 pinctrl-names = "default", "gpio"; 212 pinctrl-0 = <&pinctrl_cm40_i2c>; 213 pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; 214 scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; 215 sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; 216 status = "okay"; 217 218 wm8960: audio-codec@1a { 219 compatible = "wlf,wm8960"; 220 reg = <0x1a>; 221 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 222 clock-names = "mclk"; 223 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 224 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 225 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 226 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 227 assigned-clock-rates = <786432000>, 228 <49152000>, 229 <12288000>, 230 <12288000>; 231 wlf,shared-lrclk; 232 wlf,hp-cfg = <2 2 3>; 233 wlf,gpio-cfg = <1 3>; 234 }; 235 236 pca6416: gpio@20 { 237 compatible = "ti,tca6416"; 238 reg = <0x20>; 239 gpio-controller; 240 #gpio-cells = <2>; 241 }; 242}; 243 244&cm40_intmux { 245 status = "okay"; 246}; 247 248&lpuart0 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_lpuart0>; 251 status = "okay"; 252}; 253 254&lpuart2 { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_lpuart2>; 257 status = "okay"; 258}; 259 260&lpuart3 { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_lpuart3>; 263 status = "okay"; 264}; 265 266&mu_m0 { 267 status = "okay"; 268}; 269 270&mu1_m0 { 271 status = "okay"; 272}; 273 274&scu_key { 275 status = "okay"; 276}; 277 278&sai0 { 279 #sound-dai-cells = <0>; 280 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 281 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 282 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 283 <&sai0_lpcg IMX_LPCG_CLK_0>; 284 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_sai0>; 287 status = "okay"; 288}; 289 290&sai1 { 291 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 292 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 293 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 294 <&sai1_lpcg IMX_LPCG_CLK_0>; 295 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_sai1>; 298 status = "okay"; 299}; 300 301&sai4 { 302 assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, 303 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 304 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 305 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 306 <&sai4_lpcg IMX_LPCG_CLK_0>; 307 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 308 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 309 fsl,sai-asynchronous; 310 status = "okay"; 311}; 312 313&sai5 { 314 assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, 315 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 316 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 317 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 318 <&sai5_lpcg IMX_LPCG_CLK_0>; 319 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 320 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 321 fsl,sai-asynchronous; 322 status = "okay"; 323}; 324 325&thermal_zones { 326 pmic-thermal { 327 polling-delay-passive = <250>; 328 polling-delay = <2000>; 329 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 330 331 trips { 332 pmic_alert0: trip0 { 333 temperature = <110000>; 334 hysteresis = <2000>; 335 type = "passive"; 336 }; 337 338 pmic_crit0: trip1 { 339 temperature = <125000>; 340 hysteresis = <2000>; 341 type = "critical"; 342 }; 343 }; 344 345 cooling-maps { 346 map0 { 347 trip = <&pmic_alert0>; 348 cooling-device = 349 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 350 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 351 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 352 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 353 }; 354 }; 355 }; 356}; 357 358&usdhc1 { 359 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; 360 assigned-clock-rates = <200000000>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_usdhc1>; 363 bus-width = <8>; 364 no-sd; 365 no-sdio; 366 non-removable; 367 status = "okay"; 368}; 369 370&usdhc2 { 371 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; 372 assigned-clock-rates = <200000000>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&pinctrl_usdhc2>; 375 bus-width = <4>; 376 vmmc-supply = <®_usdhc2_vmmc>; 377 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; 378 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; 379 status = "okay"; 380}; 381 382&usb3_phy { 383 status = "okay"; 384}; 385 386&usbotg3 { 387 status = "okay"; 388}; 389 390&usbotg3_cdns3 { 391 dr_mode = "otg"; 392 usb-role-switch; 393 status = "okay"; 394 395 port { 396 usb3_drd_sw: endpoint { 397 remote-endpoint = <&typec_dr_sw>; 398 }; 399 }; 400}; 401 402 403&vpu { 404 compatible = "nxp,imx8qxp-vpu"; 405 status = "okay"; 406}; 407 408&vpu_core0 { 409 reg = <0x2d040000 0x10000>; 410 memory-region = <&decoder_boot>, <&decoder_rpc>; 411 status = "okay"; 412}; 413 414&vpu_core1 { 415 reg = <0x2d050000 0x10000>; 416 memory-region = <&encoder_boot>, <&encoder_rpc>; 417 status = "okay"; 418}; 419 420&iomuxc { 421 422 pinctrl_cm40_i2c: cm40i2cgrp { 423 fsl,pins = < 424 IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c 425 IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c 426 >; 427 }; 428 429 pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp { 430 fsl,pins = < 431 IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c 432 IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c 433 >; 434 }; 435 436 pinctrl_fec1: fec1grp { 437 fsl,pins = < 438 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 439 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 440 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 441 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 442 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 443 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 444 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 445 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 446 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 447 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 448 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 449 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 450 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 451 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 452 >; 453 }; 454 455 pinctrl_ioexp_rst: ioexprstgrp { 456 fsl,pins = < 457 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 458 >; 459 }; 460 461 pinctrl_isl29023: isl29023grp { 462 fsl,pins = < 463 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 464 >; 465 }; 466 467 pinctrl_lpi2c1: lpi2c1grp { 468 fsl,pins = < 469 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 470 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 471 >; 472 }; 473 474 pinctrl_lpuart0: lpuart0grp { 475 fsl,pins = < 476 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 477 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 478 >; 479 }; 480 481 pinctrl_lpuart2: lpuart2grp { 482 fsl,pins = < 483 IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 484 IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 485 >; 486 }; 487 488 pinctrl_lpuart3: lpuart3grp { 489 fsl,pins = < 490 IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 491 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 492 >; 493 }; 494 495 pinctrl_typec: typecgrp { 496 fsl,pins = < 497 IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 498 >; 499 }; 500 501 pinctrl_typec_mux: typecmuxgrp { 502 fsl,pins = < 503 IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 504 >; 505 }; 506 507 pinctrl_sai0: sai0grp { 508 fsl,pins = < 509 IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060 510 IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040 511 IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040 512 IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040 513 >; 514 }; 515 516 pinctrl_sai1: sai1grp { 517 fsl,pins = < 518 IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 519 IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 520 IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 521 IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 522 IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 523 >; 524 }; 525 526 pinctrl_usdhc1: usdhc1grp { 527 fsl,pins = < 528 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 529 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 530 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 531 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 532 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 533 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 534 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 535 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 536 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 537 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 538 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 539 >; 540 }; 541 542 pinctrl_usdhc2: usdhc2grp { 543 fsl,pins = < 544 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 545 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 546 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 547 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 548 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 549 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 550 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 551 >; 552 }; 553}; 554