1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/pads-imx8qm.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc0 = &usdhc1; 21 mmc1 = &usdhc2; 22 mmc2 = &usdhc3; 23 serial0 = &lpuart0; 24 serial1 = &lpuart1; 25 serial2 = &lpuart2; 26 serial3 = &lpuart3; 27 spi0 = &lpspi0; 28 spi1 = &lpspi1; 29 spi2 = &lpspi2; 30 spi3 = &lpspi3; 31 vpu-core0 = &vpu_core0; 32 vpu-core1 = &vpu_core1; 33 vpu-core2 = &vpu_core2; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu-map { 41 cluster0 { 42 core0 { 43 cpu = <&A53_0>; 44 }; 45 core1 { 46 cpu = <&A53_1>; 47 }; 48 core2 { 49 cpu = <&A53_2>; 50 }; 51 core3 { 52 cpu = <&A53_3>; 53 }; 54 }; 55 56 cluster1 { 57 core0 { 58 cpu = <&A72_0>; 59 }; 60 core1 { 61 cpu = <&A72_1>; 62 }; 63 }; 64 }; 65 66 A53_0: cpu@0 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0 0x0>; 70 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 71 enable-method = "psci"; 72 i-cache-size = <0x8000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <256>; 75 d-cache-size = <0x8000>; 76 d-cache-line-size = <64>; 77 d-cache-sets = <128>; 78 next-level-cache = <&A53_L2>; 79 operating-points-v2 = <&a53_opp_table>; 80 #cooling-cells = <2>; 81 }; 82 83 A53_1: cpu@1 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53"; 86 reg = <0x0 0x1>; 87 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <256>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&A53_L2>; 96 operating-points-v2 = <&a53_opp_table>; 97 #cooling-cells = <2>; 98 }; 99 100 A53_2: cpu@2 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x0 0x2>; 104 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 105 enable-method = "psci"; 106 i-cache-size = <0x8000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <256>; 109 d-cache-size = <0x8000>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&A53_L2>; 113 operating-points-v2 = <&a53_opp_table>; 114 #cooling-cells = <2>; 115 }; 116 117 A53_3: cpu@3 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x0 0x3>; 121 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 122 enable-method = "psci"; 123 i-cache-size = <0x8000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <256>; 126 d-cache-size = <0x8000>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&A53_L2>; 130 operating-points-v2 = <&a53_opp_table>; 131 #cooling-cells = <2>; 132 }; 133 134 A72_0: cpu@100 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a72"; 137 reg = <0x0 0x100>; 138 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; 139 enable-method = "psci"; 140 i-cache-size = <0xC000>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <256>; 143 d-cache-size = <0x8000>; 144 d-cache-line-size = <64>; 145 d-cache-sets = <256>; 146 next-level-cache = <&A72_L2>; 147 operating-points-v2 = <&a72_opp_table>; 148 #cooling-cells = <2>; 149 }; 150 151 A72_1: cpu@101 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a72"; 154 reg = <0x0 0x101>; 155 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; 156 enable-method = "psci"; 157 next-level-cache = <&A72_L2>; 158 operating-points-v2 = <&a72_opp_table>; 159 #cooling-cells = <2>; 160 }; 161 162 A53_L2: l2-cache0 { 163 compatible = "cache"; 164 cache-level = <2>; 165 cache-unified; 166 cache-size = <0x100000>; 167 cache-line-size = <64>; 168 cache-sets = <1024>; 169 }; 170 171 A72_L2: l2-cache1 { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 cache-size = <0x100000>; 176 cache-line-size = <64>; 177 cache-sets = <1024>; 178 }; 179 }; 180 181 a53_opp_table: opp-table-0 { 182 compatible = "operating-points-v2"; 183 opp-shared; 184 185 opp-600000000 { 186 opp-hz = /bits/ 64 <600000000>; 187 opp-microvolt = <900000>; 188 clock-latency-ns = <150000>; 189 }; 190 191 opp-896000000 { 192 opp-hz = /bits/ 64 <896000000>; 193 opp-microvolt = <1000000>; 194 clock-latency-ns = <150000>; 195 }; 196 197 opp-1104000000 { 198 opp-hz = /bits/ 64 <1104000000>; 199 opp-microvolt = <1100000>; 200 clock-latency-ns = <150000>; 201 }; 202 203 opp-1200000000 { 204 opp-hz = /bits/ 64 <1200000000>; 205 opp-microvolt = <1100000>; 206 clock-latency-ns = <150000>; 207 opp-suspend; 208 }; 209 }; 210 211 a72_opp_table: opp-table-1 { 212 compatible = "operating-points-v2"; 213 opp-shared; 214 215 opp-600000000 { 216 opp-hz = /bits/ 64 <600000000>; 217 opp-microvolt = <1000000>; 218 clock-latency-ns = <150000>; 219 }; 220 221 opp-1056000000 { 222 opp-hz = /bits/ 64 <1056000000>; 223 opp-microvolt = <1000000>; 224 clock-latency-ns = <150000>; 225 }; 226 227 opp-1296000000 { 228 opp-hz = /bits/ 64 <1296000000>; 229 opp-microvolt = <1100000>; 230 clock-latency-ns = <150000>; 231 }; 232 233 opp-1596000000 { 234 opp-hz = /bits/ 64 <1596000000>; 235 opp-microvolt = <1100000>; 236 clock-latency-ns = <150000>; 237 opp-suspend; 238 }; 239 }; 240 241 gic: interrupt-controller@51a00000 { 242 compatible = "arm,gic-v3"; 243 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 244 <0x0 0x51b00000 0 0xC0000>, /* GICR */ 245 <0x0 0x52000000 0 0x2000>, /* GICC */ 246 <0x0 0x52010000 0 0x1000>, /* GICH */ 247 <0x0 0x52020000 0 0x20000>; /* GICV */ 248 #interrupt-cells = <3>; 249 interrupt-controller; 250 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 251 interrupt-parent = <&gic>; 252 }; 253 254 pmu { 255 compatible = "arm,armv8-pmuv3"; 256 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 257 }; 258 259 psci { 260 compatible = "arm,psci-1.0"; 261 method = "smc"; 262 }; 263 264 timer { 265 compatible = "arm,armv8-timer"; 266 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 267 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 268 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 269 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 270 }; 271 272 smmu: iommu@51400000 { 273 compatible = "arm,mmu-500"; 274 interrupt-parent = <&gic>; 275 reg = <0 0x51400000 0 0x40000>; 276 #global-interrupts = <1>; 277 #iommu-cells = <2>; 278 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 311 }; 312 313 system-controller { 314 compatible = "fsl,imx-scu"; 315 mbox-names = "tx0", 316 "rx0", 317 "gip3"; 318 mboxes = <&lsio_mu1 0 0 319 &lsio_mu1 1 0 320 &lsio_mu1 3 3>; 321 322 pd: power-controller { 323 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; 324 #power-domain-cells = <1>; 325 }; 326 327 clk: clock-controller { 328 compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; 329 #clock-cells = <2>; 330 }; 331 332 iomuxc: pinctrl { 333 compatible = "fsl,imx8qm-iomuxc"; 334 }; 335 336 scu_reset: reset-controller { 337 compatible = "fsl,imx-scu-reset"; 338 #reset-cells = <1>; 339 }; 340 341 rtc: rtc { 342 compatible = "fsl,imx8qxp-sc-rtc"; 343 }; 344 345 ocotp: ocotp { 346 compatible = "fsl,imx8qm-scu-ocotp"; 347 #address-cells = <1>; 348 #size-cells = <1>; 349 read-only; 350 351 fec_mac0: mac@1c4 { 352 reg = <0x1c4 6>; 353 }; 354 355 fec_mac1: mac@1c6 { 356 reg = <0x1c6 6>; 357 }; 358 }; 359 360 tsens: thermal-sensor { 361 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 362 #thermal-sensor-cells = <1>; 363 }; 364 365 watchdog { 366 compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; 367 timeout-sec = <60>; 368 }; 369 }; 370 371 thermal-zones { 372 cpu0-thermal { 373 polling-delay-passive = <250>; 374 polling-delay = <2000>; 375 thermal-sensors = <&tsens IMX_SC_R_A53>; 376 377 trips { 378 cpu_alert0: trip0 { 379 temperature = <107000>; 380 hysteresis = <2000>; 381 type = "passive"; 382 }; 383 384 cpu_crit0: trip1 { 385 temperature = <127000>; 386 hysteresis = <2000>; 387 type = "critical"; 388 }; 389 }; 390 391 cooling-maps { 392 map0 { 393 trip = <&cpu_alert0>; 394 cooling-device = 395 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 396 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 397 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 398 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 399 }; 400 }; 401 }; 402 403 cpu1-thermal { 404 polling-delay-passive = <250>; 405 polling-delay = <2000>; 406 thermal-sensors = <&tsens IMX_SC_R_A72>; 407 408 trips { 409 cpu_alert1: trip0 { 410 temperature = <107000>; 411 hysteresis = <2000>; 412 type = "passive"; 413 }; 414 415 cpu_crit1: trip1 { 416 temperature = <127000>; 417 hysteresis = <2000>; 418 type = "critical"; 419 }; 420 }; 421 422 cooling-maps { 423 map0 { 424 trip = <&cpu_alert1>; 425 cooling-device = 426 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 427 <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 428 }; 429 }; 430 }; 431 432 gpu0-thermal { 433 polling-delay-passive = <250>; 434 polling-delay = <2000>; 435 thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; 436 437 trips { 438 gpu_alert0: trip0 { 439 temperature = <107000>; 440 hysteresis = <2000>; 441 type = "passive"; 442 }; 443 444 gpu_crit0: trip1 { 445 temperature = <127000>; 446 hysteresis = <2000>; 447 type = "critical"; 448 }; 449 }; 450 }; 451 452 gpu1-thermal { 453 polling-delay-passive = <250>; 454 polling-delay = <2000>; 455 thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; 456 457 trips { 458 gpu_alert1: trip0 { 459 temperature = <107000>; 460 hysteresis = <2000>; 461 type = "passive"; 462 }; 463 464 gpu_crit1: trip1 { 465 temperature = <127000>; 466 hysteresis = <2000>; 467 type = "critical"; 468 }; 469 }; 470 }; 471 472 drc0-thermal { 473 polling-delay-passive = <250>; 474 polling-delay = <2000>; 475 thermal-sensors = <&tsens IMX_SC_R_DRC_0>; 476 477 trips { 478 drc_alert0: trip0 { 479 temperature = <107000>; 480 hysteresis = <2000>; 481 type = "passive"; 482 }; 483 484 drc_crit0: trip1 { 485 temperature = <127000>; 486 hysteresis = <2000>; 487 type = "critical"; 488 }; 489 }; 490 }; 491 }; 492 493 clk_dummy: clock-dummy { 494 compatible = "fixed-clock"; 495 #clock-cells = <0>; 496 clock-frequency = <0>; 497 clock-output-names = "clk_dummy"; 498 }; 499 500 clk_esai1_rx_clk: clock-esai1-rx { 501 compatible = "fixed-clock"; 502 #clock-cells = <0>; 503 clock-frequency = <0>; 504 clock-output-names = "esai1_rx_clk"; 505 }; 506 507 clk_esai1_rx_hf_clk: clock-esai1-rx-hf { 508 compatible = "fixed-clock"; 509 #clock-cells = <0>; 510 clock-frequency = <0>; 511 clock-output-names = "esai1_rx_hf_clk"; 512 }; 513 514 clk_esai1_tx_clk: clock-esai1-tx { 515 compatible = "fixed-clock"; 516 #clock-cells = <0>; 517 clock-frequency = <0>; 518 clock-output-names = "esai1_tx_clk"; 519 }; 520 521 clk_esai1_tx_hf_clk: clock-esai1-tx-hf { 522 compatible = "fixed-clock"; 523 #clock-cells = <0>; 524 clock-frequency = <0>; 525 clock-output-names = "esai1_tx_hf_clk"; 526 }; 527 528 clk_hdmi_rx_mclk: clock-hdmi-rx-mclk { 529 compatible = "fixed-clock"; 530 #clock-cells = <0>; 531 clock-frequency = <0>; 532 clock-output-names = "hdmi-rx-mclk"; 533 }; 534 535 clk_mlb_clk: clock-mlb-clk { 536 compatible = "fixed-clock"; 537 #clock-cells = <0>; 538 clock-frequency = <0>; 539 clock-output-names = "mlb_clk"; 540 }; 541 542 clk_sai5_rx_bclk: clock-sai5-rx-bclk { 543 compatible = "fixed-clock"; 544 #clock-cells = <0>; 545 clock-frequency = <0>; 546 clock-output-names = "sai5_rx_bclk"; 547 }; 548 549 clk_sai5_tx_bclk: clock-sai5-tx-bclk { 550 compatible = "fixed-clock"; 551 #clock-cells = <0>; 552 clock-frequency = <0>; 553 clock-output-names = "sai5_tx_bclk"; 554 }; 555 556 clk_sai6_rx_bclk: clock-sai6-rx-bclk { 557 compatible = "fixed-clock"; 558 #clock-cells = <0>; 559 clock-frequency = <0>; 560 clock-output-names = "sai6_rx_bclk"; 561 }; 562 563 clk_sai6_tx_bclk: clock-sai6-tx-bclk { 564 compatible = "fixed-clock"; 565 #clock-cells = <0>; 566 clock-frequency = <0>; 567 clock-output-names = "sai6_tx_bclk"; 568 }; 569 570 clk_spdif1_rx: clock-spdif1-rx { 571 compatible = "fixed-clock"; 572 #clock-cells = <0>; 573 clock-frequency = <0>; 574 clock-output-names = "spdif1_rx"; 575 }; 576 577 lvds_ipg_clk: clock-controller-lvds-ipg { 578 compatible = "fixed-clock"; 579 #clock-cells = <0>; 580 clock-frequency = <24000000>; 581 clock-output-names = "lvds0_ipg_clk"; 582 }; 583 584 dsi_ipg_clk: clock-controller-dsi-ipg { 585 compatible = "fixed-clock"; 586 #clock-cells = <0>; 587 clock-frequency = <120000000>; 588 clock-output-names = "dsi_ipg_clk"; 589 }; 590 591 mipi_pll_div2_clk: clock-controller-mipi-div2-pll { 592 compatible = "fixed-clock"; 593 #clock-cells = <0>; 594 clock-frequency = <432000000>; 595 clock-output-names = "mipi_pll_div2_clk"; 596 }; 597 598 vpu_subsys_dsp: bus@55000000 { 599 compatible = "simple-bus"; 600 #address-cells = <1>; 601 #size-cells = <1>; 602 ranges = <0x55000000 0x0 0x55000000 0x1000000>; 603 604 vpu_dsp: dsp@556e8000 { 605 compatible = "fsl,imx8qm-hifi4"; 606 reg = <0x556e8000 0x88000>; 607 clocks = <&clk_dummy>, 608 <&clk_dummy>, 609 <&clk_dummy>; 610 clock-names = "ipg", "ocram", "core"; 611 power-domains = <&pd IMX_SC_R_MU_13B>, 612 <&pd IMX_SC_R_DSP>, 613 <&pd IMX_SC_R_DSP_RAM>, 614 <&pd IMX_SC_R_MU_2A>; 615 mboxes = <&lsio_mu13 0 0>, 616 <&lsio_mu13 1 0>, 617 <&lsio_mu13 3 0>; 618 mbox-names = "tx", "rx", "rxdb"; 619 firmware-name = "imx/dsp/hifi4.bin"; 620 status = "disabled"; 621 }; 622 }; 623 624 /* sorted in register address */ 625 #include "imx8-ss-security.dtsi" 626 #include "imx8-ss-cm41.dtsi" 627 #include "imx8-ss-audio.dtsi" 628 #include "imx8-ss-vpu.dtsi" 629 #include "imx8-ss-gpu0.dtsi" 630 #include "imx8-ss-mipi0.dtsi" 631 #include "imx8-ss-lvds0.dtsi" 632 #include "imx8-ss-mipi1.dtsi" 633 #include "imx8-ss-lvds1.dtsi" 634 #include "imx8-ss-img.dtsi" 635 #include "imx8-ss-dma.dtsi" 636 #include "imx8-ss-conn.dtsi" 637 #include "imx8-ss-lsio.dtsi" 638 #include "imx8-ss-hsio.dtsi" 639}; 640 641#include "imx8qm-ss-img.dtsi" 642#include "imx8qm-ss-dma.dtsi" 643#include "imx8qm-ss-conn.dtsi" 644#include "imx8qm-ss-lsio.dtsi" 645#include "imx8qm-ss-audio.dtsi" 646#include "imx8qm-ss-lvds.dtsi" 647#include "imx8qm-ss-mipi.dtsi" 648#include "imx8qm-ss-hsio.dtsi" 649 650/delete-node/ &dsp; 651