1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/pads-imx8qm.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc0 = &usdhc1; 21 mmc1 = &usdhc2; 22 mmc2 = &usdhc3; 23 serial0 = &lpuart0; 24 serial1 = &lpuart1; 25 serial2 = &lpuart2; 26 serial3 = &lpuart3; 27 spi0 = &lpspi0; 28 spi1 = &lpspi1; 29 spi2 = &lpspi2; 30 spi3 = &lpspi3; 31 vpu-core0 = &vpu_core0; 32 vpu-core1 = &vpu_core1; 33 vpu-core2 = &vpu_core2; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu-map { 41 cluster0 { 42 core0 { 43 cpu = <&A53_0>; 44 }; 45 core1 { 46 cpu = <&A53_1>; 47 }; 48 core2 { 49 cpu = <&A53_2>; 50 }; 51 core3 { 52 cpu = <&A53_3>; 53 }; 54 }; 55 56 cluster1 { 57 core0 { 58 cpu = <&A72_0>; 59 }; 60 core1 { 61 cpu = <&A72_1>; 62 }; 63 }; 64 }; 65 66 A53_0: cpu@0 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0 0x0>; 70 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 71 enable-method = "psci"; 72 i-cache-size = <0x8000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <256>; 75 d-cache-size = <0x8000>; 76 d-cache-line-size = <64>; 77 d-cache-sets = <128>; 78 next-level-cache = <&A53_L2>; 79 operating-points-v2 = <&a53_opp_table>; 80 #cooling-cells = <2>; 81 }; 82 83 A53_1: cpu@1 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53"; 86 reg = <0x0 0x1>; 87 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <256>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&A53_L2>; 96 operating-points-v2 = <&a53_opp_table>; 97 #cooling-cells = <2>; 98 }; 99 100 A53_2: cpu@2 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x0 0x2>; 104 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 105 enable-method = "psci"; 106 i-cache-size = <0x8000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <256>; 109 d-cache-size = <0x8000>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&A53_L2>; 113 operating-points-v2 = <&a53_opp_table>; 114 #cooling-cells = <2>; 115 }; 116 117 A53_3: cpu@3 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x0 0x3>; 121 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 122 enable-method = "psci"; 123 i-cache-size = <0x8000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <256>; 126 d-cache-size = <0x8000>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&A53_L2>; 130 operating-points-v2 = <&a53_opp_table>; 131 #cooling-cells = <2>; 132 }; 133 134 A72_0: cpu@100 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a72"; 137 reg = <0x0 0x100>; 138 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; 139 enable-method = "psci"; 140 i-cache-size = <0xC000>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <256>; 143 d-cache-size = <0x8000>; 144 d-cache-line-size = <64>; 145 d-cache-sets = <256>; 146 next-level-cache = <&A72_L2>; 147 operating-points-v2 = <&a72_opp_table>; 148 #cooling-cells = <2>; 149 }; 150 151 A72_1: cpu@101 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a72"; 154 reg = <0x0 0x101>; 155 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; 156 enable-method = "psci"; 157 next-level-cache = <&A72_L2>; 158 operating-points-v2 = <&a72_opp_table>; 159 #cooling-cells = <2>; 160 }; 161 162 A53_L2: l2-cache0 { 163 compatible = "cache"; 164 cache-level = <2>; 165 cache-unified; 166 cache-size = <0x100000>; 167 cache-line-size = <64>; 168 cache-sets = <1024>; 169 }; 170 171 A72_L2: l2-cache1 { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 cache-size = <0x100000>; 176 cache-line-size = <64>; 177 cache-sets = <1024>; 178 }; 179 }; 180 181 a53_opp_table: opp-table-0 { 182 compatible = "operating-points-v2"; 183 opp-shared; 184 185 opp-600000000 { 186 opp-hz = /bits/ 64 <600000000>; 187 opp-microvolt = <900000>; 188 clock-latency-ns = <150000>; 189 }; 190 191 opp-896000000 { 192 opp-hz = /bits/ 64 <896000000>; 193 opp-microvolt = <1000000>; 194 clock-latency-ns = <150000>; 195 }; 196 197 opp-1104000000 { 198 opp-hz = /bits/ 64 <1104000000>; 199 opp-microvolt = <1100000>; 200 clock-latency-ns = <150000>; 201 }; 202 203 opp-1200000000 { 204 opp-hz = /bits/ 64 <1200000000>; 205 opp-microvolt = <1100000>; 206 clock-latency-ns = <150000>; 207 opp-suspend; 208 }; 209 }; 210 211 a72_opp_table: opp-table-1 { 212 compatible = "operating-points-v2"; 213 opp-shared; 214 215 opp-600000000 { 216 opp-hz = /bits/ 64 <600000000>; 217 opp-microvolt = <1000000>; 218 clock-latency-ns = <150000>; 219 }; 220 221 opp-1056000000 { 222 opp-hz = /bits/ 64 <1056000000>; 223 opp-microvolt = <1000000>; 224 clock-latency-ns = <150000>; 225 }; 226 227 opp-1296000000 { 228 opp-hz = /bits/ 64 <1296000000>; 229 opp-microvolt = <1100000>; 230 clock-latency-ns = <150000>; 231 }; 232 233 opp-1596000000 { 234 opp-hz = /bits/ 64 <1596000000>; 235 opp-microvolt = <1100000>; 236 clock-latency-ns = <150000>; 237 opp-suspend; 238 }; 239 }; 240 241 gic: interrupt-controller@51a00000 { 242 compatible = "arm,gic-v3"; 243 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 244 <0x0 0x51b00000 0 0xC0000>, /* GICR */ 245 <0x0 0x52000000 0 0x2000>, /* GICC */ 246 <0x0 0x52010000 0 0x1000>, /* GICH */ 247 <0x0 0x52020000 0 0x20000>; /* GICV */ 248 #address-cells = <0>; 249 #interrupt-cells = <3>; 250 interrupt-controller; 251 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-parent = <&gic>; 253 }; 254 255 pmu { 256 compatible = "arm,armv8-pmuv3"; 257 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 258 }; 259 260 psci { 261 compatible = "arm,psci-1.0"; 262 method = "smc"; 263 }; 264 265 timer { 266 compatible = "arm,armv8-timer"; 267 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 268 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 269 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 270 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 271 }; 272 273 smmu: iommu@51400000 { 274 compatible = "arm,mmu-500"; 275 interrupt-parent = <&gic>; 276 reg = <0 0x51400000 0 0x40000>; 277 #global-interrupts = <1>; 278 #iommu-cells = <2>; 279 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 312 }; 313 314 system-controller { 315 compatible = "fsl,imx-scu"; 316 mbox-names = "tx0", 317 "rx0", 318 "gip3"; 319 mboxes = <&lsio_mu1 0 0 320 &lsio_mu1 1 0 321 &lsio_mu1 3 3>; 322 323 pd: power-controller { 324 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; 325 #power-domain-cells = <1>; 326 }; 327 328 clk: clock-controller { 329 compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; 330 #clock-cells = <2>; 331 }; 332 333 iomuxc: pinctrl { 334 compatible = "fsl,imx8qm-iomuxc"; 335 }; 336 337 scu_reset: reset-controller { 338 compatible = "fsl,imx-scu-reset"; 339 #reset-cells = <1>; 340 }; 341 342 rtc: rtc { 343 compatible = "fsl,imx8qxp-sc-rtc"; 344 }; 345 346 ocotp: ocotp { 347 compatible = "fsl,imx8qm-scu-ocotp"; 348 #address-cells = <1>; 349 #size-cells = <1>; 350 read-only; 351 352 fec_mac0: mac@1c4 { 353 reg = <0x1c4 6>; 354 }; 355 356 fec_mac1: mac@1c6 { 357 reg = <0x1c6 6>; 358 }; 359 }; 360 361 tsens: thermal-sensor { 362 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 363 #thermal-sensor-cells = <1>; 364 }; 365 366 watchdog { 367 compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; 368 timeout-sec = <60>; 369 }; 370 }; 371 372 thermal-zones { 373 cpu0-thermal { 374 polling-delay-passive = <250>; 375 polling-delay = <2000>; 376 thermal-sensors = <&tsens IMX_SC_R_A53>; 377 378 trips { 379 cpu_alert0: trip0 { 380 temperature = <107000>; 381 hysteresis = <2000>; 382 type = "passive"; 383 }; 384 385 cpu_crit0: trip1 { 386 temperature = <127000>; 387 hysteresis = <2000>; 388 type = "critical"; 389 }; 390 }; 391 392 cooling-maps { 393 map0 { 394 trip = <&cpu_alert0>; 395 cooling-device = 396 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 397 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 398 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 399 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 400 }; 401 }; 402 }; 403 404 cpu1-thermal { 405 polling-delay-passive = <250>; 406 polling-delay = <2000>; 407 thermal-sensors = <&tsens IMX_SC_R_A72>; 408 409 trips { 410 cpu_alert1: trip0 { 411 temperature = <107000>; 412 hysteresis = <2000>; 413 type = "passive"; 414 }; 415 416 cpu_crit1: trip1 { 417 temperature = <127000>; 418 hysteresis = <2000>; 419 type = "critical"; 420 }; 421 }; 422 423 cooling-maps { 424 map0 { 425 trip = <&cpu_alert1>; 426 cooling-device = 427 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 428 <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 429 }; 430 }; 431 }; 432 433 gpu0-thermal { 434 polling-delay-passive = <250>; 435 polling-delay = <2000>; 436 thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; 437 438 trips { 439 gpu_alert0: trip0 { 440 temperature = <107000>; 441 hysteresis = <2000>; 442 type = "passive"; 443 }; 444 445 gpu_crit0: trip1 { 446 temperature = <127000>; 447 hysteresis = <2000>; 448 type = "critical"; 449 }; 450 }; 451 }; 452 453 gpu1-thermal { 454 polling-delay-passive = <250>; 455 polling-delay = <2000>; 456 thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; 457 458 trips { 459 gpu_alert1: trip0 { 460 temperature = <107000>; 461 hysteresis = <2000>; 462 type = "passive"; 463 }; 464 465 gpu_crit1: trip1 { 466 temperature = <127000>; 467 hysteresis = <2000>; 468 type = "critical"; 469 }; 470 }; 471 }; 472 473 drc0-thermal { 474 polling-delay-passive = <250>; 475 polling-delay = <2000>; 476 thermal-sensors = <&tsens IMX_SC_R_DRC_0>; 477 478 trips { 479 drc_alert0: trip0 { 480 temperature = <107000>; 481 hysteresis = <2000>; 482 type = "passive"; 483 }; 484 485 drc_crit0: trip1 { 486 temperature = <127000>; 487 hysteresis = <2000>; 488 type = "critical"; 489 }; 490 }; 491 }; 492 }; 493 494 clk_dummy: clock-dummy { 495 compatible = "fixed-clock"; 496 #clock-cells = <0>; 497 clock-frequency = <0>; 498 clock-output-names = "clk_dummy"; 499 }; 500 501 clk_esai1_rx_clk: clock-esai1-rx { 502 compatible = "fixed-clock"; 503 #clock-cells = <0>; 504 clock-frequency = <0>; 505 clock-output-names = "esai1_rx_clk"; 506 }; 507 508 clk_esai1_rx_hf_clk: clock-esai1-rx-hf { 509 compatible = "fixed-clock"; 510 #clock-cells = <0>; 511 clock-frequency = <0>; 512 clock-output-names = "esai1_rx_hf_clk"; 513 }; 514 515 clk_esai1_tx_clk: clock-esai1-tx { 516 compatible = "fixed-clock"; 517 #clock-cells = <0>; 518 clock-frequency = <0>; 519 clock-output-names = "esai1_tx_clk"; 520 }; 521 522 clk_esai1_tx_hf_clk: clock-esai1-tx-hf { 523 compatible = "fixed-clock"; 524 #clock-cells = <0>; 525 clock-frequency = <0>; 526 clock-output-names = "esai1_tx_hf_clk"; 527 }; 528 529 clk_hdmi_rx_mclk: clock-hdmi-rx-mclk { 530 compatible = "fixed-clock"; 531 #clock-cells = <0>; 532 clock-frequency = <0>; 533 clock-output-names = "hdmi-rx-mclk"; 534 }; 535 536 clk_mlb_clk: clock-mlb-clk { 537 compatible = "fixed-clock"; 538 #clock-cells = <0>; 539 clock-frequency = <0>; 540 clock-output-names = "mlb_clk"; 541 }; 542 543 clk_sai5_rx_bclk: clock-sai5-rx-bclk { 544 compatible = "fixed-clock"; 545 #clock-cells = <0>; 546 clock-frequency = <0>; 547 clock-output-names = "sai5_rx_bclk"; 548 }; 549 550 clk_sai5_tx_bclk: clock-sai5-tx-bclk { 551 compatible = "fixed-clock"; 552 #clock-cells = <0>; 553 clock-frequency = <0>; 554 clock-output-names = "sai5_tx_bclk"; 555 }; 556 557 clk_sai6_rx_bclk: clock-sai6-rx-bclk { 558 compatible = "fixed-clock"; 559 #clock-cells = <0>; 560 clock-frequency = <0>; 561 clock-output-names = "sai6_rx_bclk"; 562 }; 563 564 clk_sai6_tx_bclk: clock-sai6-tx-bclk { 565 compatible = "fixed-clock"; 566 #clock-cells = <0>; 567 clock-frequency = <0>; 568 clock-output-names = "sai6_tx_bclk"; 569 }; 570 571 clk_spdif1_rx: clock-spdif1-rx { 572 compatible = "fixed-clock"; 573 #clock-cells = <0>; 574 clock-frequency = <0>; 575 clock-output-names = "spdif1_rx"; 576 }; 577 578 lvds_ipg_clk: clock-controller-lvds-ipg { 579 compatible = "fixed-clock"; 580 #clock-cells = <0>; 581 clock-frequency = <24000000>; 582 clock-output-names = "lvds0_ipg_clk"; 583 }; 584 585 dsi_ipg_clk: clock-controller-dsi-ipg { 586 compatible = "fixed-clock"; 587 #clock-cells = <0>; 588 clock-frequency = <120000000>; 589 clock-output-names = "dsi_ipg_clk"; 590 }; 591 592 mipi_pll_div2_clk: clock-controller-mipi-div2-pll { 593 compatible = "fixed-clock"; 594 #clock-cells = <0>; 595 clock-frequency = <432000000>; 596 clock-output-names = "mipi_pll_div2_clk"; 597 }; 598 599 vpu_subsys_dsp: bus@55000000 { 600 compatible = "simple-bus"; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 ranges = <0x55000000 0x0 0x55000000 0x1000000>; 604 605 vpu_dsp: dsp@556e8000 { 606 compatible = "fsl,imx8qm-hifi4"; 607 reg = <0x556e8000 0x88000>; 608 clocks = <&clk_dummy>, 609 <&clk_dummy>, 610 <&clk_dummy>; 611 clock-names = "ipg", "ocram", "core"; 612 power-domains = <&pd IMX_SC_R_MU_13B>, 613 <&pd IMX_SC_R_DSP>, 614 <&pd IMX_SC_R_DSP_RAM>, 615 <&pd IMX_SC_R_MU_2A>; 616 mboxes = <&lsio_mu13 0 0>, 617 <&lsio_mu13 1 0>, 618 <&lsio_mu13 3 0>; 619 mbox-names = "tx", "rx", "rxdb"; 620 firmware-name = "imx/dsp/hifi4.bin"; 621 status = "disabled"; 622 }; 623 }; 624 625 /* sorted in register address */ 626 #include "imx8-ss-security.dtsi" 627 #include "imx8-ss-cm41.dtsi" 628 #include "imx8-ss-audio.dtsi" 629 #include "imx8-ss-vpu.dtsi" 630 #include "imx8-ss-gpu0.dtsi" 631 #include "imx8-ss-mipi0.dtsi" 632 #include "imx8-ss-lvds0.dtsi" 633 #include "imx8-ss-mipi1.dtsi" 634 #include "imx8-ss-lvds1.dtsi" 635 #include "imx8-ss-img.dtsi" 636 #include "imx8-ss-dma.dtsi" 637 #include "imx8-ss-conn.dtsi" 638 #include "imx8-ss-lsio.dtsi" 639 #include "imx8-ss-hsio.dtsi" 640}; 641 642#include "imx8qm-ss-img.dtsi" 643#include "imx8qm-ss-dma.dtsi" 644#include "imx8qm-ss-conn.dtsi" 645#include "imx8qm-ss-lsio.dtsi" 646#include "imx8qm-ss-audio.dtsi" 647#include "imx8qm-ss-lvds.dtsi" 648#include "imx8qm-ss-mipi.dtsi" 649#include "imx8qm-ss-hsio.dtsi" 650 651/delete-node/ &dsp; 652