1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/pads-imx8qm.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc0 = &usdhc1; 21 mmc1 = &usdhc2; 22 mmc2 = &usdhc3; 23 serial0 = &lpuart0; 24 serial1 = &lpuart1; 25 serial2 = &lpuart2; 26 serial3 = &lpuart3; 27 vpu-core0 = &vpu_core0; 28 vpu-core1 = &vpu_core1; 29 vpu-core2 = &vpu_core2; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu-map { 37 cluster0 { 38 core0 { 39 cpu = <&A53_0>; 40 }; 41 core1 { 42 cpu = <&A53_1>; 43 }; 44 core2 { 45 cpu = <&A53_2>; 46 }; 47 core3 { 48 cpu = <&A53_3>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&A72_0>; 55 }; 56 core1 { 57 cpu = <&A72_1>; 58 }; 59 }; 60 }; 61 62 A53_0: cpu@0 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0x0 0x0>; 66 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 67 enable-method = "psci"; 68 i-cache-size = <0x8000>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <256>; 71 d-cache-size = <0x8000>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <128>; 74 next-level-cache = <&A53_L2>; 75 operating-points-v2 = <&a53_opp_table>; 76 #cooling-cells = <2>; 77 }; 78 79 A53_1: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x0 0x1>; 83 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 84 enable-method = "psci"; 85 i-cache-size = <0x8000>; 86 i-cache-line-size = <64>; 87 i-cache-sets = <256>; 88 d-cache-size = <0x8000>; 89 d-cache-line-size = <64>; 90 d-cache-sets = <128>; 91 next-level-cache = <&A53_L2>; 92 operating-points-v2 = <&a53_opp_table>; 93 #cooling-cells = <2>; 94 }; 95 96 A53_2: cpu@2 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x2>; 100 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 101 enable-method = "psci"; 102 i-cache-size = <0x8000>; 103 i-cache-line-size = <64>; 104 i-cache-sets = <256>; 105 d-cache-size = <0x8000>; 106 d-cache-line-size = <64>; 107 d-cache-sets = <128>; 108 next-level-cache = <&A53_L2>; 109 operating-points-v2 = <&a53_opp_table>; 110 #cooling-cells = <2>; 111 }; 112 113 A53_3: cpu@3 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a53"; 116 reg = <0x0 0x3>; 117 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; 118 enable-method = "psci"; 119 i-cache-size = <0x8000>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <256>; 122 d-cache-size = <0x8000>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&A53_L2>; 126 operating-points-v2 = <&a53_opp_table>; 127 #cooling-cells = <2>; 128 }; 129 130 A72_0: cpu@100 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a72"; 133 reg = <0x0 0x100>; 134 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; 135 enable-method = "psci"; 136 i-cache-size = <0xC000>; 137 i-cache-line-size = <64>; 138 i-cache-sets = <256>; 139 d-cache-size = <0x8000>; 140 d-cache-line-size = <64>; 141 d-cache-sets = <256>; 142 next-level-cache = <&A72_L2>; 143 operating-points-v2 = <&a72_opp_table>; 144 #cooling-cells = <2>; 145 }; 146 147 A72_1: cpu@101 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a72"; 150 reg = <0x0 0x101>; 151 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; 152 enable-method = "psci"; 153 next-level-cache = <&A72_L2>; 154 operating-points-v2 = <&a72_opp_table>; 155 #cooling-cells = <2>; 156 }; 157 158 A53_L2: l2-cache0 { 159 compatible = "cache"; 160 cache-level = <2>; 161 cache-unified; 162 cache-size = <0x100000>; 163 cache-line-size = <64>; 164 cache-sets = <1024>; 165 }; 166 167 A72_L2: l2-cache1 { 168 compatible = "cache"; 169 cache-level = <2>; 170 cache-unified; 171 cache-size = <0x100000>; 172 cache-line-size = <64>; 173 cache-sets = <1024>; 174 }; 175 }; 176 177 a53_opp_table: opp-table-0 { 178 compatible = "operating-points-v2"; 179 opp-shared; 180 181 opp-600000000 { 182 opp-hz = /bits/ 64 <600000000>; 183 opp-microvolt = <900000>; 184 clock-latency-ns = <150000>; 185 }; 186 187 opp-896000000 { 188 opp-hz = /bits/ 64 <896000000>; 189 opp-microvolt = <1000000>; 190 clock-latency-ns = <150000>; 191 }; 192 193 opp-1104000000 { 194 opp-hz = /bits/ 64 <1104000000>; 195 opp-microvolt = <1100000>; 196 clock-latency-ns = <150000>; 197 }; 198 199 opp-1200000000 { 200 opp-hz = /bits/ 64 <1200000000>; 201 opp-microvolt = <1100000>; 202 clock-latency-ns = <150000>; 203 opp-suspend; 204 }; 205 }; 206 207 a72_opp_table: opp-table-1 { 208 compatible = "operating-points-v2"; 209 opp-shared; 210 211 opp-600000000 { 212 opp-hz = /bits/ 64 <600000000>; 213 opp-microvolt = <1000000>; 214 clock-latency-ns = <150000>; 215 }; 216 217 opp-1056000000 { 218 opp-hz = /bits/ 64 <1056000000>; 219 opp-microvolt = <1000000>; 220 clock-latency-ns = <150000>; 221 }; 222 223 opp-1296000000 { 224 opp-hz = /bits/ 64 <1296000000>; 225 opp-microvolt = <1100000>; 226 clock-latency-ns = <150000>; 227 }; 228 229 opp-1596000000 { 230 opp-hz = /bits/ 64 <1596000000>; 231 opp-microvolt = <1100000>; 232 clock-latency-ns = <150000>; 233 opp-suspend; 234 }; 235 }; 236 237 gic: interrupt-controller@51a00000 { 238 compatible = "arm,gic-v3"; 239 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 240 <0x0 0x51b00000 0 0xC0000>, /* GICR */ 241 <0x0 0x52000000 0 0x2000>, /* GICC */ 242 <0x0 0x52010000 0 0x1000>, /* GICH */ 243 <0x0 0x52020000 0 0x20000>; /* GICV */ 244 #interrupt-cells = <3>; 245 interrupt-controller; 246 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 247 interrupt-parent = <&gic>; 248 }; 249 250 pmu { 251 compatible = "arm,armv8-pmuv3"; 252 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 253 }; 254 255 psci { 256 compatible = "arm,psci-1.0"; 257 method = "smc"; 258 }; 259 260 timer { 261 compatible = "arm,armv8-timer"; 262 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 263 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 264 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 265 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 266 }; 267 268 smmu: iommu@51400000 { 269 compatible = "arm,mmu-500"; 270 interrupt-parent = <&gic>; 271 reg = <0 0x51400000 0 0x40000>; 272 #global-interrupts = <1>; 273 #iommu-cells = <2>; 274 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 307 }; 308 309 system-controller { 310 compatible = "fsl,imx-scu"; 311 mbox-names = "tx0", 312 "rx0", 313 "gip3"; 314 mboxes = <&lsio_mu1 0 0 315 &lsio_mu1 1 0 316 &lsio_mu1 3 3>; 317 318 pd: power-controller { 319 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; 320 #power-domain-cells = <1>; 321 }; 322 323 clk: clock-controller { 324 compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; 325 #clock-cells = <2>; 326 }; 327 328 iomuxc: pinctrl { 329 compatible = "fsl,imx8qm-iomuxc"; 330 }; 331 332 rtc: rtc { 333 compatible = "fsl,imx8qxp-sc-rtc"; 334 }; 335 336 ocotp: ocotp { 337 compatible = "fsl,imx8qm-scu-ocotp"; 338 #address-cells = <1>; 339 #size-cells = <1>; 340 read-only; 341 342 fec_mac0: mac@1c4 { 343 reg = <0x1c4 6>; 344 }; 345 346 fec_mac1: mac@1c6 { 347 reg = <0x1c6 6>; 348 }; 349 }; 350 351 tsens: thermal-sensor { 352 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 353 #thermal-sensor-cells = <1>; 354 }; 355 }; 356 357 thermal-zones { 358 cpu0-thermal { 359 polling-delay-passive = <250>; 360 polling-delay = <2000>; 361 thermal-sensors = <&tsens IMX_SC_R_A53>; 362 363 trips { 364 cpu_alert0: trip0 { 365 temperature = <107000>; 366 hysteresis = <2000>; 367 type = "passive"; 368 }; 369 370 cpu_crit0: trip1 { 371 temperature = <127000>; 372 hysteresis = <2000>; 373 type = "critical"; 374 }; 375 }; 376 377 cooling-maps { 378 map0 { 379 trip = <&cpu_alert0>; 380 cooling-device = 381 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 382 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 383 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 384 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 385 }; 386 }; 387 }; 388 389 cpu1-thermal { 390 polling-delay-passive = <250>; 391 polling-delay = <2000>; 392 thermal-sensors = <&tsens IMX_SC_R_A72>; 393 394 trips { 395 cpu_alert1: trip0 { 396 temperature = <107000>; 397 hysteresis = <2000>; 398 type = "passive"; 399 }; 400 401 cpu_crit1: trip1 { 402 temperature = <127000>; 403 hysteresis = <2000>; 404 type = "critical"; 405 }; 406 }; 407 408 cooling-maps { 409 map0 { 410 trip = <&cpu_alert1>; 411 cooling-device = 412 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 413 <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 414 }; 415 }; 416 }; 417 418 gpu0-thermal { 419 polling-delay-passive = <250>; 420 polling-delay = <2000>; 421 thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; 422 423 trips { 424 gpu_alert0: trip0 { 425 temperature = <107000>; 426 hysteresis = <2000>; 427 type = "passive"; 428 }; 429 430 gpu_crit0: trip1 { 431 temperature = <127000>; 432 hysteresis = <2000>; 433 type = "critical"; 434 }; 435 }; 436 }; 437 438 gpu1-thermal { 439 polling-delay-passive = <250>; 440 polling-delay = <2000>; 441 thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; 442 443 trips { 444 gpu_alert1: trip0 { 445 temperature = <107000>; 446 hysteresis = <2000>; 447 type = "passive"; 448 }; 449 450 gpu_crit1: trip1 { 451 temperature = <127000>; 452 hysteresis = <2000>; 453 type = "critical"; 454 }; 455 }; 456 }; 457 458 drc0-thermal { 459 polling-delay-passive = <250>; 460 polling-delay = <2000>; 461 thermal-sensors = <&tsens IMX_SC_R_DRC_0>; 462 463 trips { 464 drc_alert0: trip0 { 465 temperature = <107000>; 466 hysteresis = <2000>; 467 type = "passive"; 468 }; 469 470 drc_crit0: trip1 { 471 temperature = <127000>; 472 hysteresis = <2000>; 473 type = "critical"; 474 }; 475 }; 476 }; 477 }; 478 479 clk_dummy: clock-dummy { 480 compatible = "fixed-clock"; 481 #clock-cells = <0>; 482 clock-frequency = <0>; 483 clock-output-names = "clk_dummy"; 484 }; 485 486 clk_esai1_rx_clk: clock-esai1-rx { 487 compatible = "fixed-clock"; 488 #clock-cells = <0>; 489 clock-frequency = <0>; 490 clock-output-names = "esai1_rx_clk"; 491 }; 492 493 clk_esai1_rx_hf_clk: clock-esai1-rx-hf { 494 compatible = "fixed-clock"; 495 #clock-cells = <0>; 496 clock-frequency = <0>; 497 clock-output-names = "esai1_rx_hf_clk"; 498 }; 499 500 clk_esai1_tx_clk: clock-esai1-tx { 501 compatible = "fixed-clock"; 502 #clock-cells = <0>; 503 clock-frequency = <0>; 504 clock-output-names = "esai1_tx_clk"; 505 }; 506 507 clk_esai1_tx_hf_clk: clock-esai1-tx-hf { 508 compatible = "fixed-clock"; 509 #clock-cells = <0>; 510 clock-frequency = <0>; 511 clock-output-names = "esai1_tx_hf_clk"; 512 }; 513 514 clk_hdmi_rx_mclk: clock-hdmi-rx-mclk { 515 compatible = "fixed-clock"; 516 #clock-cells = <0>; 517 clock-frequency = <0>; 518 clock-output-names = "hdmi-rx-mclk"; 519 }; 520 521 clk_mlb_clk: clock-mlb-clk { 522 compatible = "fixed-clock"; 523 #clock-cells = <0>; 524 clock-frequency = <0>; 525 clock-output-names = "mlb_clk"; 526 }; 527 528 clk_sai5_rx_bclk: clock-sai5-rx-bclk { 529 compatible = "fixed-clock"; 530 #clock-cells = <0>; 531 clock-frequency = <0>; 532 clock-output-names = "sai5_rx_bclk"; 533 }; 534 535 clk_sai5_tx_bclk: clock-sai5-tx-bclk { 536 compatible = "fixed-clock"; 537 #clock-cells = <0>; 538 clock-frequency = <0>; 539 clock-output-names = "sai5_tx_bclk"; 540 }; 541 542 clk_sai6_rx_bclk: clock-sai6-rx-bclk { 543 compatible = "fixed-clock"; 544 #clock-cells = <0>; 545 clock-frequency = <0>; 546 clock-output-names = "sai6_rx_bclk"; 547 }; 548 549 clk_sai6_tx_bclk: clock-sai6-tx-bclk { 550 compatible = "fixed-clock"; 551 #clock-cells = <0>; 552 clock-frequency = <0>; 553 clock-output-names = "sai6_tx_bclk"; 554 }; 555 556 clk_spdif1_rx: clock-spdif1-rx { 557 compatible = "fixed-clock"; 558 #clock-cells = <0>; 559 clock-frequency = <0>; 560 clock-output-names = "spdif1_rx"; 561 }; 562 563 lvds_ipg_clk: clock-controller-lvds-ipg { 564 compatible = "fixed-clock"; 565 #clock-cells = <0>; 566 clock-frequency = <24000000>; 567 clock-output-names = "lvds0_ipg_clk"; 568 }; 569 570 dsi_ipg_clk: clock-controller-dsi-ipg { 571 compatible = "fixed-clock"; 572 #clock-cells = <0>; 573 clock-frequency = <120000000>; 574 clock-output-names = "dsi_ipg_clk"; 575 }; 576 577 mipi_pll_div2_clk: clock-controller-mipi-div2-pll { 578 compatible = "fixed-clock"; 579 #clock-cells = <0>; 580 clock-frequency = <432000000>; 581 clock-output-names = "mipi_pll_div2_clk"; 582 }; 583 584 /* sorted in register address */ 585 #include "imx8-ss-cm41.dtsi" 586 #include "imx8-ss-audio.dtsi" 587 #include "imx8-ss-vpu.dtsi" 588 #include "imx8-ss-gpu0.dtsi" 589 #include "imx8-ss-mipi0.dtsi" 590 #include "imx8-ss-lvds0.dtsi" 591 #include "imx8-ss-mipi1.dtsi" 592 #include "imx8-ss-lvds1.dtsi" 593 #include "imx8-ss-img.dtsi" 594 #include "imx8-ss-dma.dtsi" 595 #include "imx8-ss-conn.dtsi" 596 #include "imx8-ss-lsio.dtsi" 597}; 598 599#include "imx8qm-ss-img.dtsi" 600#include "imx8qm-ss-dma.dtsi" 601#include "imx8qm-ss-conn.dtsi" 602#include "imx8qm-ss-lsio.dtsi" 603#include "imx8qm-ss-audio.dtsi" 604#include "imx8qm-ss-lvds.dtsi" 605#include "imx8qm-ss-mipi.dtsi" 606