1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2024 NXP 4 * Richard Zhu <hongxing.zhu@nxp.com> 5 */ 6 7&hsio_subsys { 8 compatible = "simple-bus"; 9 ranges = <0x5f000000 0x0 0x5f000000 0x01000000>, 10 <0x40000000 0x0 0x60000000 0x10000000>, 11 <0x80000000 0x0 0x70000000 0x10000000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 pciea: pcie@5f000000 { 16 compatible = "fsl,imx8q-pcie"; 17 reg = <0x5f000000 0x10000>, 18 <0x4ff00000 0x80000>; 19 reg-names = "dbi", "config"; 20 ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>, 21 <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; 22 #interrupt-cells = <1>; 23 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-names = "msi"; 25 #address-cells = <3>; 26 #size-cells = <2>; 27 clocks = <&pciea_lpcg IMX_LPCG_CLK_6>, 28 <&pciea_lpcg IMX_LPCG_CLK_4>, 29 <&pciea_lpcg IMX_LPCG_CLK_5>; 30 clock-names = "dbi", "mstr", "slv"; 31 bus-range = <0x00 0xff>; 32 device_type = "pci"; 33 interrupt-map = <0 0 0 1 &gic 0 73 4>, 34 <0 0 0 2 &gic 0 74 4>, 35 <0 0 0 3 &gic 0 75 4>, 36 <0 0 0 4 &gic 0 76 4>; 37 interrupt-map-mask = <0 0 0 0x7>; 38 num-lanes = <1>; 39 num-viewport = <4>; 40 power-domains = <&pd IMX_SC_R_PCIE_A>; 41 fsl,max-link-speed = <3>; 42 status = "disabled"; 43 }; 44 45 pcieb: pcie@5f010000 { 46 compatible = "fsl,imx8q-pcie"; 47 reg = <0x5f010000 0x10000>, 48 <0x8ff00000 0x80000>; 49 reg-names = "dbi", "config"; 50 ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, 51 <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; 52 #interrupt-cells = <1>; 53 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 54 interrupt-names = "msi"; 55 #address-cells = <3>; 56 #size-cells = <2>; 57 clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, 58 <&pcieb_lpcg IMX_LPCG_CLK_4>, 59 <&pcieb_lpcg IMX_LPCG_CLK_5>; 60 clock-names = "dbi", "mstr", "slv"; 61 bus-range = <0x00 0xff>; 62 device_type = "pci"; 63 interrupt-map = <0 0 0 1 &gic 0 105 4>, 64 <0 0 0 2 &gic 0 106 4>, 65 <0 0 0 3 &gic 0 107 4>, 66 <0 0 0 4 &gic 0 108 4>; 67 interrupt-map-mask = <0 0 0 0x7>; 68 num-lanes = <1>; 69 num-viewport = <4>; 70 power-domains = <&pd IMX_SC_R_PCIE_B>; 71 fsl,max-link-speed = <3>; 72 status = "disabled"; 73 }; 74 75 sata: sata@5f020000 { 76 compatible = "fsl,imx8qm-ahci"; 77 reg = <0x5f020000 0x10000>; 78 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&sata_lpcg IMX_LPCG_CLK_4>, 80 <&sata_crr4_lpcg IMX_LPCG_CLK_4>; 81 clock-names = "sata", "sata_ref"; 82 phy-names = "sata-phy", "cali-phy0", "cali-phy1"; 83 power-domains = <&pd IMX_SC_R_SATA_0>; 84 /* 85 * Since "REXT" pin is only present for first lane PHY 86 * and its calibration result will be stored, and shared 87 * by the PHY used by SATA. 88 * 89 * Add the calibration PHYs for SATA here, although only 90 * the third lane PHY is used by SATA. 91 */ 92 phys = <&hsio_phy 2 PHY_TYPE_SATA 0>, 93 <&hsio_phy 0 PHY_TYPE_PCIE 0>, 94 <&hsio_phy 1 PHY_TYPE_PCIE 1>; 95 status = "disabled"; 96 }; 97 98 pciea_lpcg: clock-controller@5f050000 { 99 compatible = "fsl,imx8qxp-lpcg"; 100 reg = <0x5f050000 0x10000>; 101 clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; 102 #clock-cells = <1>; 103 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; 104 clock-output-names = "hsio_pciea_mstr_axi_clk", 105 "hsio_pciea_slv_axi_clk", 106 "hsio_pciea_dbi_axi_clk"; 107 power-domains = <&pd IMX_SC_R_PCIE_A>; 108 }; 109 110 sata_lpcg: clock-controller@5f070000 { 111 compatible = "fsl,imx8qxp-lpcg"; 112 reg = <0x5f070000 0x10000>; 113 clocks = <&hsio_axi_clk>; 114 #clock-cells = <1>; 115 clock-indices = <IMX_LPCG_CLK_4>; 116 clock-output-names = "hsio_sata_clk"; 117 power-domains = <&pd IMX_SC_R_SATA_0>; 118 }; 119 120 phyx2_lpcg: clock-controller@5f080000 { 121 compatible = "fsl,imx8qxp-lpcg"; 122 reg = <0x5f080000 0x10000>; 123 clocks = <&hsio_refa_clk>, <&hsio_per_clk>, 124 <&hsio_refa_clk>, <&hsio_per_clk>; 125 #clock-cells = <1>; 126 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 127 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 128 clock-output-names = "hsio_phyx2_pclk_0", 129 "hsio_phyx2_pclk_1", 130 "hsio_phyx2_apbclk_0", 131 "hsio_phyx2_apbclk_1"; 132 power-domains = <&pd IMX_SC_R_SERDES_0>; 133 }; 134 135 phyx1_lpcg: clock-controller@5f090000 { 136 compatible = "fsl,imx8qxp-lpcg"; 137 reg = <0x5f090000 0x10000>; 138 clocks = <&hsio_refa_clk>, <&hsio_per_clk>, 139 <&hsio_per_clk>, <&hsio_per_clk>; 140 #clock-cells = <1>; 141 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 142 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>; 143 clock-output-names = "hsio_phyx1_pclk", 144 "hsio_phyx1_epcs_tx_clk", 145 "hsio_phyx1_epcs_rx_clk", 146 "hsio_phyx1_apb_clk"; 147 power-domains = <&pd IMX_SC_R_SERDES_1>; 148 }; 149 150 phyx2_crr0_lpcg: clock-controller@5f0a0000 { 151 compatible = "fsl,imx8qxp-lpcg"; 152 reg = <0x5f0a0000 0x10000>; 153 clocks = <&hsio_per_clk>; 154 #clock-cells = <1>; 155 clock-indices = <IMX_LPCG_CLK_4>; 156 clock-output-names = "hsio_phyx2_per_clk"; 157 power-domains = <&pd IMX_SC_R_SERDES_0>; 158 }; 159 160 pciea_crr2_lpcg: clock-controller@5f0c0000 { 161 compatible = "fsl,imx8qxp-lpcg"; 162 reg = <0x5f0c0000 0x10000>; 163 clocks = <&hsio_per_clk>; 164 #clock-cells = <1>; 165 clock-indices = <IMX_LPCG_CLK_4>; 166 clock-output-names = "hsio_pciea_per_clk"; 167 power-domains = <&pd IMX_SC_R_PCIE_A>; 168 }; 169 170 sata_crr4_lpcg: clock-controller@5f0e0000 { 171 compatible = "fsl,imx8qxp-lpcg"; 172 reg = <0x5f0e0000 0x10000>; 173 clocks = <&hsio_per_clk>; 174 #clock-cells = <1>; 175 clock-indices = <IMX_LPCG_CLK_4>; 176 clock-output-names = "hsio_sata_per_clk"; 177 power-domains = <&pd IMX_SC_R_SATA_0>; 178 }; 179 180 hsio_phy: phy@5f180000 { 181 compatible = "fsl,imx8qm-hsio"; 182 reg = <0x5f180000 0x30000>, 183 <0x5f110000 0x20000>, 184 <0x5f130000 0x30000>, 185 <0x5f160000 0x10000>; 186 reg-names = "reg", "phy", "ctrl", "misc"; 187 clocks = <&phyx2_lpcg IMX_LPCG_CLK_0>, 188 <&phyx2_lpcg IMX_LPCG_CLK_1>, 189 <&phyx2_lpcg IMX_LPCG_CLK_4>, 190 <&phyx2_lpcg IMX_LPCG_CLK_5>, 191 <&phyx1_lpcg IMX_LPCG_CLK_0>, 192 <&phyx1_lpcg IMX_LPCG_CLK_1>, 193 <&phyx1_lpcg IMX_LPCG_CLK_2>, 194 <&phyx1_lpcg IMX_LPCG_CLK_4>, 195 <&phyx2_crr0_lpcg IMX_LPCG_CLK_4>, 196 <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, 197 <&pciea_crr2_lpcg IMX_LPCG_CLK_4>, 198 <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, 199 <&sata_crr4_lpcg IMX_LPCG_CLK_4>, 200 <&misc_crr5_lpcg IMX_LPCG_CLK_4>; 201 clock-names = "pclk0", "pclk1", "apb_pclk0", "apb_pclk1", 202 "pclk2", "epcs_tx", "epcs_rx", "apb_pclk2", 203 "phy0_crr", "phy1_crr", "ctl0_crr", 204 "ctl1_crr", "ctl2_crr", "misc_crr"; 205 #phy-cells = <3>; 206 power-domains = <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_SERDES_1>; 207 status = "disabled"; 208 }; 209}; 210