1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7&dma_subsys { 8 uart4_lpcg: clock-controller@5a4a0000 { 9 compatible = "fsl,imx8qxp-lpcg"; 10 reg = <0x5a4a0000 0x10000>; 11 #clock-cells = <1>; 12 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, 13 <&dma_ipg_clk>; 14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 15 clock-output-names = "uart4_lpcg_baud_clk", 16 "uart4_lpcg_ipg_clk"; 17 power-domains = <&pd IMX_SC_R_UART_4>; 18 }; 19 20 i2c4: i2c@5a840000 { 21 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 22 reg = <0x5a840000 0x4000>; 23 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-parent = <&gic>; 25 clocks = <&i2c4_lpcg 0>, 26 <&i2c4_lpcg 1>; 27 clock-names = "per", "ipg"; 28 assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>; 29 assigned-clock-rates = <24000000>; 30 power-domains = <&pd IMX_SC_R_I2C_4>; 31 status = "disabled"; 32 }; 33 34 i2c4_lpcg: clock-controller@5ac40000 { 35 compatible = "fsl,imx8qxp-lpcg"; 36 reg = <0x5ac40000 0x10000>; 37 #clock-cells = <1>; 38 clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>, 39 <&dma_ipg_clk>; 40 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 41 clock-output-names = "i2c4_lpcg_clk", 42 "i2c4_lpcg_ipg_clk"; 43 power-domains = <&pd IMX_SC_R_I2C_4>; 44 }; 45 46 can1_lpcg: clock-controller@5ace0000 { 47 compatible = "fsl,imx8qxp-lpcg"; 48 reg = <0x5ace0000 0x10000>; 49 #clock-cells = <1>; 50 clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, 51 <&dma_ipg_clk>, <&dma_ipg_clk>; 52 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 53 clock-output-names = "can1_lpcg_pe_clk", 54 "can1_lpcg_ipg_clk", 55 "can1_lpcg_chi_clk"; 56 power-domains = <&pd IMX_SC_R_CAN_1>; 57 }; 58 59 can2_lpcg: clock-controller@5acf0000 { 60 compatible = "fsl,imx8qxp-lpcg"; 61 reg = <0x5acf0000 0x10000>; 62 #clock-cells = <1>; 63 clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, 64 <&dma_ipg_clk>, <&dma_ipg_clk>; 65 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 66 clock-output-names = "can2_lpcg_pe_clk", 67 "can2_lpcg_ipg_clk", 68 "can2_lpcg_chi_clk"; 69 power-domains = <&pd IMX_SC_R_CAN_2>; 70 }; 71}; 72 73&edma2 { 74 reg = <0x5a1f0000 0x170000>; 75 #dma-cells = <3>; 76 dma-channels = <22>; 77 dma-channel-mask = <0xf00>; 78 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ 87 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ 88 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ 89 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ 90 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 100 power-domains = <&pd IMX_SC_R_DMA_0_CH0>, 101 <&pd IMX_SC_R_DMA_0_CH1>, 102 <&pd IMX_SC_R_DMA_0_CH2>, 103 <&pd IMX_SC_R_DMA_0_CH3>, 104 <&pd IMX_SC_R_DMA_0_CH4>, 105 <&pd IMX_SC_R_DMA_0_CH5>, 106 <&pd IMX_SC_R_DMA_0_CH6>, 107 <&pd IMX_SC_R_DMA_0_CH7>, 108 <&pd IMX_SC_R_DMA_0_CH8>, 109 <&pd IMX_SC_R_DMA_0_CH9>, 110 <&pd IMX_SC_R_DMA_0_CH10>, 111 <&pd IMX_SC_R_DMA_0_CH11>, 112 <&pd IMX_SC_R_DMA_0_CH12>, 113 <&pd IMX_SC_R_DMA_0_CH13>, 114 <&pd IMX_SC_R_DMA_0_CH14>, 115 <&pd IMX_SC_R_DMA_0_CH15>, 116 <&pd IMX_SC_R_DMA_0_CH16>, 117 <&pd IMX_SC_R_DMA_0_CH17>, 118 <&pd IMX_SC_R_DMA_0_CH18>, 119 <&pd IMX_SC_R_DMA_0_CH19>, 120 <&pd IMX_SC_R_DMA_0_CH20>, 121 <&pd IMX_SC_R_DMA_0_CH21>; 122 status = "okay"; 123}; 124 125/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */ 126&edma3 { 127 reg = <0x5a9f0000 0x210000>; 128 dma-channels = <10>; 129 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; 139 power-domains = <&pd IMX_SC_R_DMA_1_CH0>, 140 <&pd IMX_SC_R_DMA_1_CH1>, 141 <&pd IMX_SC_R_DMA_1_CH2>, 142 <&pd IMX_SC_R_DMA_1_CH3>, 143 <&pd IMX_SC_R_DMA_1_CH4>, 144 <&pd IMX_SC_R_DMA_1_CH5>, 145 <&pd IMX_SC_R_DMA_1_CH6>, 146 <&pd IMX_SC_R_DMA_1_CH7>, 147 <&pd IMX_SC_R_DMA_1_CH8>, 148 <&pd IMX_SC_R_DMA_1_CH9>; 149}; 150 151&flexcan1 { 152 fsl,clk-source = /bits/ 8 <1>; 153}; 154 155&flexcan2 { 156 clocks = <&can1_lpcg 1>, 157 <&can1_lpcg 0>; 158 assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; 159 fsl,clk-source = /bits/ 8 <1>; 160}; 161 162&flexcan3 { 163 clocks = <&can2_lpcg 1>, 164 <&can2_lpcg 0>; 165 assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; 166 fsl,clk-source = /bits/ 8 <1>; 167}; 168 169&lpuart0 { 170 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 171 dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; 172 dma-names = "rx","tx"; 173}; 174 175&lpuart1 { 176 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 177 dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; 178 dma-names = "rx","tx"; 179}; 180 181&lpuart2 { 182 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 183 dmas = <&edma2 17 0 0>, <&edma2 16 0 1>; 184 dma-names = "rx","tx"; 185}; 186 187&lpuart3 { 188 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 189 dmas = <&edma2 19 0 0>, <&edma2 18 0 1>; 190 dma-names = "rx","tx"; 191}; 192 193&i2c0 { 194 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 195}; 196 197&i2c1 { 198 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 199}; 200 201&i2c2 { 202 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 203}; 204 205&i2c3 { 206 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 207}; 208