1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/usb/pd.h> 10#include "imx8qm.dtsi" 11 12/ { 13 model = "Freescale i.MX8QM MEK"; 14 compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; 15 16 chosen { 17 stdout-path = &lpuart0; 18 }; 19 20 cpus { 21 /delete-node/ cpu-map; 22 /delete-node/ cpu@100; 23 /delete-node/ cpu@101; 24 }; 25 26 thermal-zones { 27 /delete-node/ cpu1-thermal; 28 }; 29 30 memory@80000000 { 31 device_type = "memory"; 32 reg = <0x00000000 0x80000000 0 0x40000000>; 33 }; 34 35 xtal24m: clock-xtal24m { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <24000000>; 39 clock-output-names = "xtal_24MHz"; 40 }; 41 42 reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 vdev0vring0: memory@90000000 { 48 reg = <0 0x90000000 0 0x8000>; 49 no-map; 50 }; 51 52 vdev0vring1: memory@90008000 { 53 reg = <0 0x90008000 0 0x8000>; 54 no-map; 55 }; 56 57 vdev1vring0: memory@90010000 { 58 reg = <0 0x90010000 0 0x8000>; 59 no-map; 60 }; 61 62 vdev1vring1: memory@90018000 { 63 reg = <0 0x90018000 0 0x8000>; 64 no-map; 65 }; 66 67 rsc_table0: memory@900ff000 { 68 reg = <0 0x900ff000 0 0x1000>; 69 no-map; 70 }; 71 72 vdev2vring0: memory@90100000 { 73 reg = <0 0x90100000 0 0x8000>; 74 no-map; 75 }; 76 77 vdev2vring1: memory@90108000 { 78 reg = <0 0x90108000 0 0x8000>; 79 no-map; 80 }; 81 82 vdev3vring0: memory@90110000 { 83 reg = <0 0x90110000 0 0x8000>; 84 no-map; 85 }; 86 87 vdev3vring1: memory@90118000 { 88 reg = <0 0x90118000 0 0x8000>; 89 no-map; 90 }; 91 92 rsc_table1: memory@901ff000 { 93 reg = <0 0x901ff000 0 0x1000>; 94 no-map; 95 }; 96 97 vdevbuffer: memory@90400000 { 98 compatible = "shared-dma-pool"; 99 reg = <0 0x90400000 0 0x100000>; 100 no-map; 101 }; 102 103 dsp_reserved: memory@92400000 { 104 reg = <0 0x92400000 0 0x1000000>; 105 no-map; 106 }; 107 108 dsp_vdev0vring0: memory@942f0000 { 109 reg = <0 0x942f0000 0 0x8000>; 110 no-map; 111 }; 112 113 dsp_vdev0vring1: memory@942f8000 { 114 reg = <0 0x942f8000 0 0x8000>; 115 no-map; 116 }; 117 118 dsp_vdev0buffer: memory@94300000 { 119 compatible = "shared-dma-pool"; 120 reg = <0 0x94300000 0 0x100000>; 121 no-map; 122 }; 123 124 /* global autoconfigured region for contiguous allocations */ 125 linux,cma { 126 compatible = "shared-dma-pool"; 127 alloc-ranges = <0 0xc0000000 0 0x3c000000>; 128 size = <0 0x3c000000>; 129 linux,cma-default; 130 reusable; 131 }; 132 }; 133 134 lvds_backlight0: backlight-lvds0 { 135 compatible = "pwm-backlight"; 136 pwms = <&qm_pwm_lvds0 0 100000 0>; 137 brightness-levels = <0 100>; 138 num-interpolated-steps = <100>; 139 default-brightness-level = <80>; 140 }; 141 142 lvds_backlight1: backlight-lvds1 { 143 compatible = "pwm-backlight"; 144 pwms = <&pwm_lvds1 0 100000 0>; 145 brightness-levels = <0 100>; 146 num-interpolated-steps = <100>; 147 default-brightness-level = <80>; 148 }; 149 150 i2c-mux { 151 compatible = "i2c-mux-gpio"; 152 mux-gpios = <&lsio_gpio5 3 GPIO_ACTIVE_HIGH>; /* needs to be an unused GPIO */ 153 i2c-parent = <&i2c1>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 i2c@0 { 158 reg = <0>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 162 wm8960: audio-codec@1a { 163 compatible = "wlf,wm8960"; 164 reg = <0x1a>; 165 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 166 clock-names = "mclk"; 167 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 168 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 169 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 170 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 171 assigned-clock-rates = <786432000>, 172 <49152000>, 173 <12288000>, 174 <12288000>; 175 wlf,shared-lrclk; 176 wlf,hp-cfg = <2 2 3>; 177 wlf,gpio-cfg = <1 3>; 178 AVDD-supply = <®_audio_3v3>; 179 DBVDD-supply = <®_audio_1v8>; 180 DCVDD-supply = <®_audio_1v8>; 181 SPKVDD1-supply = <®_audio_5v>; 182 SPKVDD2-supply = <®_audio_5v>; 183 }; 184 }; 185 186 i2c@1 { 187 reg = <1>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 wm8962: wm8962@1a { 192 compatible = "wlf,wm8962"; 193 reg = <0x1a>; 194 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 195 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 196 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 197 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 198 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 199 assigned-clock-rates = <786432000>, 200 <49152000>, 201 <12288000>, 202 <12288000>; 203 DCVDD-supply = <®_audio_1v8>; 204 DBVDD-supply = <®_audio_1v8>; 205 AVDD-supply = <®_audio_1v8>; 206 CPVDD-supply = <®_audio_1v8>; 207 MICVDD-supply = <®_audio_3v3>; 208 PLLVDD-supply = <®_audio_1v8>; 209 SPKVDD1-supply = <®_audio_5v>; 210 SPKVDD2-supply = <®_audio_5v>; 211 }; 212 }; 213 214 }; 215 216 mux-controller { 217 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_typec_mux>; 220 select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; 221 enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 222 orientation-switch; 223 224 port { 225 usb3_data_ss: endpoint { 226 remote-endpoint = <&typec_con_ss>; 227 }; 228 }; 229 }; 230 231 reg_1v5: regulator-1v5 { 232 compatible = "regulator-fixed"; 233 regulator-name = "1v5"; 234 regulator-min-microvolt = <1500000>; 235 regulator-max-microvolt = <1500000>; 236 }; 237 238 reg_1v8: regulator-1v8 { 239 compatible = "regulator-fixed"; 240 regulator-name = "1v8"; 241 regulator-min-microvolt = <1800000>; 242 regulator-max-microvolt = <1800000>; 243 }; 244 245 reg_2v8: regulator-2v8 { 246 compatible = "regulator-fixed"; 247 regulator-name = "2v8"; 248 regulator-min-microvolt = <2800000>; 249 regulator-max-microvolt = <2800000>; 250 }; 251 252 reg_usdhc2_vmmc: usdhc2-vmmc { 253 compatible = "regulator-fixed"; 254 regulator-name = "SD1_SPWR"; 255 regulator-min-microvolt = <3000000>; 256 regulator-max-microvolt = <3000000>; 257 gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; 258 enable-active-high; 259 }; 260 261 reg_audio: regulator-audio { 262 compatible = "regulator-fixed"; 263 regulator-name = "cs42888_supply"; 264 regulator-min-microvolt = <3300000>; 265 regulator-max-microvolt = <3300000>; 266 }; 267 268 reg_fec2_supply: regulator-fec2-nvcc { 269 compatible = "regulator-fixed"; 270 regulator-name = "fec2_nvcc"; 271 regulator-min-microvolt = <1800000>; 272 regulator-max-microvolt = <1800000>; 273 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; 274 enable-active-high; 275 }; 276 277 reg_can01_en: regulator-can01-gen { 278 compatible = "regulator-fixed"; 279 regulator-name = "can01-en"; 280 regulator-min-microvolt = <3300000>; 281 regulator-max-microvolt = <3300000>; 282 gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; 283 enable-active-high; 284 }; 285 286 reg_can2_en: regulator-can2-gen { 287 compatible = "regulator-fixed"; 288 regulator-name = "can2-en"; 289 regulator-min-microvolt = <3300000>; 290 regulator-max-microvolt = <3300000>; 291 gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; 292 enable-active-high; 293 }; 294 295 reg_can01_stby: regulator-can01-stby { 296 compatible = "regulator-fixed"; 297 regulator-name = "can01-stby"; 298 regulator-min-microvolt = <3300000>; 299 regulator-max-microvolt = <3300000>; 300 gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; 301 enable-active-high; 302 vin-supply = <®_can01_en>; 303 }; 304 305 reg_can2_stby: regulator-can2-stby { 306 compatible = "regulator-fixed"; 307 regulator-name = "can2-stby"; 308 regulator-min-microvolt = <3300000>; 309 regulator-max-microvolt = <3300000>; 310 gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; 311 enable-active-high; 312 vin-supply = <®_can2_en>; 313 }; 314 315 reg_pciea: regulator-pcie { 316 compatible = "regulator-fixed"; 317 pinctrl-0 = <&pinctrl_pciea_reg>; 318 pinctrl-names = "default"; 319 regulator-max-microvolt = <3300000>; 320 regulator-min-microvolt = <3300000>; 321 regulator-name = "mpcie_3v3"; 322 gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; 323 enable-active-high; 324 }; 325 326 reg_vref_1v8: regulator-adc-vref { 327 compatible = "regulator-fixed"; 328 regulator-name = "vref_1v8"; 329 regulator-min-microvolt = <1800000>; 330 regulator-max-microvolt = <1800000>; 331 }; 332 333 reg_audio_5v: regulator-audio-pwr { 334 compatible = "regulator-fixed"; 335 regulator-name = "audio-5v"; 336 regulator-min-microvolt = <5000000>; 337 regulator-max-microvolt = <5000000>; 338 regulator-always-on; 339 regulator-boot-on; 340 }; 341 342 reg_audio_3v3: regulator-audio-3v3 { 343 compatible = "regulator-fixed"; 344 regulator-name = "audio-3v3"; 345 regulator-min-microvolt = <3300000>; 346 regulator-max-microvolt = <3300000>; 347 regulator-always-on; 348 regulator-boot-on; 349 }; 350 351 reg_audio_1v8: regulator-audio-1v8 { 352 compatible = "regulator-fixed"; 353 regulator-name = "audio-1v8"; 354 regulator-min-microvolt = <1800000>; 355 regulator-max-microvolt = <1800000>; 356 regulator-always-on; 357 regulator-boot-on; 358 }; 359 360 bt_sco_codec: audio-codec-bt { 361 compatible = "linux,bt-sco"; 362 #sound-dai-cells = <1>; 363 }; 364 365 sound-bt-sco { 366 compatible = "simple-audio-card"; 367 simple-audio-card,name = "bt-sco-audio"; 368 simple-audio-card,format = "dsp_a"; 369 simple-audio-card,bitclock-inversion; 370 simple-audio-card,frame-master = <&btcpu>; 371 simple-audio-card,bitclock-master = <&btcpu>; 372 373 btcpu: simple-audio-card,cpu { 374 sound-dai = <&sai0>; 375 dai-tdm-slot-num = <2>; 376 dai-tdm-slot-width = <16>; 377 }; 378 379 simple-audio-card,codec { 380 sound-dai = <&bt_sco_codec 1>; 381 }; 382 }; 383 384 sound-cs42888 { 385 compatible = "fsl,imx-audio-cs42888"; 386 model = "imx-cs42888"; 387 audio-cpu = <&esai0>; 388 audio-codec = <&cs42888>; 389 audio-asrc = <&asrc0>; 390 audio-routing = "Line Out Jack", "AOUT1L", 391 "Line Out Jack", "AOUT1R", 392 "Line Out Jack", "AOUT2L", 393 "Line Out Jack", "AOUT2R", 394 "Line Out Jack", "AOUT3L", 395 "Line Out Jack", "AOUT3R", 396 "Line Out Jack", "AOUT4L", 397 "Line Out Jack", "AOUT4R", 398 "AIN1L", "Line In Jack", 399 "AIN1R", "Line In Jack", 400 "AIN2L", "Line In Jack", 401 "AIN2R", "Line In Jack"; 402 }; 403 404 sound-wm8960 { 405 compatible = "fsl,imx-audio-wm8960"; 406 model = "wm8960-audio"; 407 audio-cpu = <&sai1>; 408 audio-codec = <&wm8960>; 409 hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; 410 audio-routing = "Headphone Jack", "HP_L", 411 "Headphone Jack", "HP_R", 412 "Ext Spk", "SPK_LP", 413 "Ext Spk", "SPK_LN", 414 "Ext Spk", "SPK_RP", 415 "Ext Spk", "SPK_RN", 416 "LINPUT1", "Mic Jack", 417 "Mic Jack", "MICB"; 418 }; 419 420 sound-wm8962 { 421 compatible = "fsl,imx-audio-wm8962"; 422 model = "wm8962-audio"; 423 audio-cpu = <&sai1>; 424 audio-codec = <&wm8962>; 425 hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; 426 audio-routing = "Headphone Jack", "HPOUTL", 427 "Headphone Jack", "HPOUTR", 428 "Ext Spk", "SPKOUTL", 429 "Ext Spk", "SPKOUTR", 430 "AMIC", "MICBIAS", 431 "IN1R", "AMIC", 432 "IN3R", "AMIC"; 433 }; 434 435 imx8qm-cm4-0 { 436 compatible = "fsl,imx8qm-cm4"; 437 clocks = <&clk_dummy>; 438 mbox-names = "tx", "rx", "rxdb"; 439 mboxes = <&lsio_mu5 0 1 440 &lsio_mu5 1 1 441 &lsio_mu5 3 1>; 442 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 443 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>; 444 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; 445 446 fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 447 fsl,entry-address = <0x34fe0000>; 448 }; 449 450 imx8qm-cm4-1 { 451 compatible = "fsl,imx8qm-cm4"; 452 clocks = <&clk_dummy>; 453 mbox-names = "tx", "rx", "rxdb"; 454 mboxes = <&lsio_mu6 0 1 455 &lsio_mu6 1 1 456 &lsio_mu6 3 1>; 457 memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>, 458 <&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>; 459 power-domains = <&pd IMX_SC_R_M4_1_PID0>, <&pd IMX_SC_R_M4_1_MU_1A>; 460 461 fsl,resource-id = <IMX_SC_R_M4_1_PID0>; 462 fsl,entry-address = <0x38fe0000>; 463 }; 464 465}; 466 467&adc0 { 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_adc0>; 470 vref-supply = <®_vref_1v8>; 471 status = "okay"; 472}; 473 474&amix { 475 status = "okay"; 476}; 477 478&asrc0 { 479 fsl,asrc-rate = <48000>; 480 status = "okay"; 481}; 482 483&cm41_i2c { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 clock-frequency = <100000>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pinctrl_cm41_i2c>; 489 status = "okay"; 490 491 pca6416: gpio@20 { 492 compatible = "ti,tca6416"; 493 reg = <0x20>; 494 gpio-controller; 495 #gpio-cells = <2>; 496 }; 497 498 cs42888: audio-codec@48 { 499 compatible = "cirrus,cs42888"; 500 reg = <0x48>; 501 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 502 clock-names = "mclk"; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&pinctrl_cs42888_reset>; 505 VA-supply = <®_audio>; 506 VD-supply = <®_audio>; 507 VLS-supply = <®_audio>; 508 VLC-supply = <®_audio>; 509 reset-gpios = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; 510 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 511 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 512 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 513 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 514 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 515 }; 516}; 517 518&cm41_intmux { 519 status = "okay"; 520}; 521 522&esai0 { 523 pinctrl-names = "default"; 524 pinctrl-0 = <&pinctrl_esai0>; 525 assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, 526 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 527 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 528 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 529 <&esai0_lpcg IMX_LPCG_CLK_4>; 530 assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; 531 assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; 532 status = "okay"; 533}; 534 535&hsio_phy { 536 fsl,hsio-cfg = "pciea-pcieb-sata"; 537 fsl,refclk-pad-mode = "input"; 538 status = "okay"; 539}; 540 541&i2c0 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 clock-frequency = <100000>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&pinctrl_i2c0>; 547 status = "okay"; 548 549 accelerometer@19 { 550 compatible = "st,lsm303agr-accel"; 551 reg = <0x19>; 552 }; 553 554 gyrometer@20 { 555 compatible = "nxp,fxas21002c"; 556 reg = <0x20>; 557 }; 558 559 light-sensor@44 { 560 compatible = "isil,isl29023"; 561 reg = <0x44>; 562 interrupt-parent = <&lsio_gpio4>; 563 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 564 }; 565 566 pressure-sensor@60 { 567 compatible = "fsl,mpl3115"; 568 reg = <0x60>; 569 }; 570 571 max7322: gpio@68 { 572 compatible = "maxim,max7322"; 573 reg = <0x68>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 }; 577 578 gyrometer@69 { 579 compatible = "st,l3g4200d-gyro"; 580 reg = <0x69>; 581 }; 582 583 ptn5110: tcpc@51 { 584 compatible = "nxp,ptn5110", "tcpci"; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&pinctrl_typec>; 587 reg = <0x51>; 588 interrupt-parent = <&lsio_gpio4>; 589 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 590 status = "okay"; 591 592 usb_con1: connector { 593 compatible = "usb-c-connector"; 594 label = "USB-C"; 595 power-role = "source"; 596 data-role = "dual"; 597 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 598 599 ports { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 603 port@0 { 604 reg = <0>; 605 606 typec_dr_sw: endpoint { 607 remote-endpoint = <&usb3_drd_sw>; 608 }; 609 }; 610 611 port@1 { 612 reg = <1>; 613 typec_con_ss: endpoint { 614 remote-endpoint = <&usb3_data_ss>; 615 }; 616 }; 617 }; 618 }; 619 }; 620}; 621 622&i2c1 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 clock-frequency = <100000>; 626 pinctrl-names = "default", "gpio"; 627 pinctrl-0 = <&pinctrl_i2c1>; 628 pinctrl-1 = <&pinctrl_i2c1_gpio>; 629 scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; 630 sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; 631 status = "okay"; 632}; 633 634&i2c1_lvds0 { 635 pinctrl-names = "default"; 636 pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; 637 clock-frequency = <100000>; 638 status = "okay"; 639}; 640 641&i2c1_lvds1 { 642 pinctrl-names = "default"; 643 pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; 644 clock-frequency = <100000>; 645 status = "okay"; 646}; 647 648&i2c0_mipi0 { 649 pinctrl-names = "default"; 650 pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; 651 clock-frequency = <100000>; 652 status = "okay"; 653}; 654 655&i2c0_mipi1 { 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; 658 clock-frequency = <100000>; 659 status = "okay"; 660}; 661 662&flexcan1 { 663 pinctrl-names = "default"; 664 pinctrl-0 = <&pinctrl_flexcan1>; 665 xceiver-supply = <®_can01_stby>; 666 status = "okay"; 667}; 668 669&flexcan2 { 670 pinctrl-names = "default"; 671 pinctrl-0 = <&pinctrl_flexcan2>; 672 xceiver-supply = <®_can01_stby>; 673 status = "okay"; 674}; 675 676&flexcan3 { 677 pinctrl-names = "default"; 678 pinctrl-0 = <&pinctrl_flexcan3>; 679 xceiver-supply = <®_can2_stby>; 680 status = "okay"; 681}; 682 683&lpuart0 { 684 pinctrl-names = "default"; 685 pinctrl-0 = <&pinctrl_lpuart0>; 686 status = "okay"; 687}; 688 689&lpuart2 { 690 pinctrl-names = "default"; 691 pinctrl-0 = <&pinctrl_lpuart2>; 692 status = "okay"; 693}; 694 695&lpuart3 { 696 pinctrl-names = "default"; 697 pinctrl-0 = <&pinctrl_lpuart3>; 698 status = "okay"; 699}; 700 701&lpspi2 { 702 #address-cells = <1>; 703 #size-cells = <0>; 704 pinctrl-names = "default"; 705 pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; 706 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; 707 status = "okay"; 708}; 709 710&lsio_mu5 { 711 status = "okay"; 712}; 713 714&lsio_mu6 { 715 status = "okay"; 716}; 717 718&flexspi0 { 719 pinctrl-names = "default"; 720 pinctrl-0 = <&pinctrl_flexspi0>; 721 status = "okay"; 722 723 flash0: flash@0 { 724 reg = <0>; 725 #address-cells = <1>; 726 #size-cells = <1>; 727 compatible = "jedec,spi-nor"; 728 spi-max-frequency = <133000000>; 729 spi-tx-bus-width = <8>; 730 spi-rx-bus-width = <8>; 731 }; 732}; 733 734&fec1 { 735 pinctrl-names = "default"; 736 pinctrl-0 = <&pinctrl_fec1>; 737 phy-mode = "rgmii-id"; 738 phy-handle = <ðphy0>; 739 fsl,magic-packet; 740 status = "okay"; 741 742 mdio { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 746 ethphy0: ethernet-phy@0 { 747 compatible = "ethernet-phy-ieee802.3-c22"; 748 reg = <0>; 749 }; 750 751 ethphy1: ethernet-phy@1 { 752 compatible = "ethernet-phy-ieee802.3-c22"; 753 reg = <1>; 754 }; 755 }; 756}; 757 758&fec2 { 759 pinctrl-names = "default"; 760 pinctrl-0 = <&pinctrl_fec2>; 761 phy-mode = "rgmii-txid"; 762 phy-handle = <ðphy1>; 763 phy-supply = <®_fec2_supply>; 764 nvmem-cells = <&fec_mac1>; 765 nvmem-cell-names = "mac-address"; 766 rx-internal-delay-ps = <2000>; 767 fsl,magic-packet; 768 status = "okay"; 769}; 770 771&pciea { 772 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 773 phy-names = "pcie-phy"; 774 pinctrl-0 = <&pinctrl_pciea>; 775 pinctrl-names = "default"; 776 reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; 777 vpcie-supply = <®_pciea>; 778 status = "okay"; 779}; 780 781&pcieb { 782 phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; 783 phy-names = "pcie-phy"; 784 pinctrl-0 = <&pinctrl_pcieb>; 785 pinctrl-names = "default"; 786 reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; 787 status = "disabled"; 788}; 789 790&qm_pwm_lvds0 { 791 pinctrl-names = "default"; 792 pinctrl-0 = <&pinctrl_pwm_lvds0>; 793 status = "okay"; 794}; 795 796&pwm_lvds1 { 797 pinctrl-names = "default"; 798 pinctrl-0 = <&pinctrl_pwm_lvds1>; 799 status = "okay"; 800}; 801 802&usdhc1 { 803 pinctrl-names = "default"; 804 pinctrl-0 = <&pinctrl_usdhc1>; 805 bus-width = <8>; 806 no-sd; 807 no-sdio; 808 non-removable; 809 status = "okay"; 810}; 811 812&usdhc2 { 813 pinctrl-names = "default"; 814 pinctrl-0 = <&pinctrl_usdhc2>; 815 bus-width = <4>; 816 vmmc-supply = <®_usdhc2_vmmc>; 817 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; 818 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; 819 status = "okay"; 820}; 821 822&usb3_phy { 823 status = "okay"; 824}; 825 826&usbotg3 { 827 status = "okay"; 828}; 829 830&usbotg3_cdns3 { 831 dr_mode = "otg"; 832 usb-role-switch; 833 status = "okay"; 834 835 port { 836 usb3_drd_sw: endpoint { 837 remote-endpoint = <&typec_dr_sw>; 838 }; 839 }; 840}; 841 842&sai0 { 843 #sound-dai-cells = <0>; 844 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 845 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 846 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 847 <&sai0_lpcg IMX_LPCG_CLK_4>; 848 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 849 pinctrl-names = "default"; 850 pinctrl-0 = <&pinctrl_sai0>; 851 status = "okay"; 852}; 853 854&sai1 { 855 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 856 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 857 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 858 <&sai1_lpcg IMX_LPCG_CLK_4>; 859 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&pinctrl_sai1>; 862 status = "okay"; 863}; 864 865&sai6 { 866 assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, 867 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 868 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 869 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 870 <&sai6_lpcg IMX_LPCG_CLK_4>; 871 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 872 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 873 fsl,sai-asynchronous; 874 status = "okay"; 875}; 876 877&sai7 { 878 assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, 879 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 880 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 881 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 882 <&sai7_lpcg IMX_LPCG_CLK_4>; 883 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 884 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 885 fsl,sai-asynchronous; 886 status = "okay"; 887}; 888 889&sata { 890 status = "okay"; 891}; 892 893&vpu_dsp { 894 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 895 <&dsp_vdev0vring1>, <&dsp_reserved>; 896 status = "okay"; 897}; 898 899&iomuxc { 900 pinctrl-names = "default"; 901 pinctrl-0 = <&pinctrl_hog>; 902 903 pinctrl_hog: hoggrp { 904 fsl,pins = < 905 IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c 906 IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c 907 >; 908 }; 909 910 pinctrl_cs42888_reset: cs42888_resetgrp { 911 fsl,pins = < 912 IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c 913 >; 914 }; 915 916 pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp { 917 fsl,pins = < 918 IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 919 IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 920 >; 921 }; 922 923 pinctrl_i2c_mipi_csi1: i2c-mipi-csi1grp { 924 fsl,pins = < 925 IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 926 IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 927 >; 928 }; 929 930 pinctrl_i2c0: i2c0grp { 931 fsl,pins = < 932 IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 933 IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 934 >; 935 }; 936 937 pinctrl_i2c1: i2c1grp { 938 fsl,pins = < 939 IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c 940 IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c 941 >; 942 }; 943 944 pinctrl_i2c1_gpio: i2c1gpio-grp { 945 fsl,pins = < 946 IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c 947 IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c 948 >; 949 }; 950 951 pinctrl_adc0: adc0grp { 952 fsl,pins = < 953 IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 954 >; 955 }; 956 957 pinctrl_cm41_i2c: cm41i2cgrp { 958 fsl,pins = < 959 IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c 960 IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c 961 >; 962 }; 963 964 pinctrl_esai0: esai0grp { 965 fsl,pins = < 966 IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 967 IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 968 IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 969 IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 970 IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 971 IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 972 IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 973 IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 974 IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 975 IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 976 >; 977 }; 978 979 pinctrl_fec1: fec1grp { 980 fsl,pins = < 981 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 982 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 983 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 984 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 985 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 986 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 987 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 988 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 989 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 990 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 991 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 992 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 993 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 994 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 995 >; 996 }; 997 998 pinctrl_lpspi2: lpspi2grp { 999 fsl,pins = < 1000 IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040 1001 IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040 1002 IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040 1003 >; 1004 }; 1005 1006 pinctrl_lpspi2_cs: lpspi2csgrp { 1007 fsl,pins = < 1008 IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 1009 >; 1010 }; 1011 1012 pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { 1013 fsl,pins = < 1014 IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 1015 IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 1016 IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 1017 >; 1018 }; 1019 1020 pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { 1021 fsl,pins = < 1022 IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 1023 IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 1024 IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 1025 >; 1026 }; 1027 1028 pinctrl_flexspi0: flexspi0grp { 1029 fsl,pins = < 1030 IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 1031 IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 1032 IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 1033 IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 1034 IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 1035 IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 1036 IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 1037 IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 1038 IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 1039 IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 1040 IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 1041 IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 1042 IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 1043 IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 1044 IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 1045 IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 1046 >; 1047 }; 1048 1049 pinctrl_fec2: fec2grp { 1050 fsl,pins = < 1051 IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 1052 IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 1053 IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 1054 IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 1055 IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 1056 IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 1057 IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 1058 IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 1059 IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 1060 IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 1061 IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 1062 IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 1063 IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 1064 >; 1065 }; 1066 1067 pinctrl_flexcan1: flexcan0grp { 1068 fsl,pins = < 1069 IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 1070 IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 1071 >; 1072 }; 1073 1074 pinctrl_flexcan2: flexcan1grp { 1075 fsl,pins = < 1076 IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 1077 IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 1078 >; 1079 }; 1080 1081 pinctrl_flexcan3: flexcan3grp { 1082 fsl,pins = < 1083 IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 1084 IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 1085 >; 1086 }; 1087 1088 pinctrl_lpuart0: lpuart0grp { 1089 fsl,pins = < 1090 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 1091 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 1092 >; 1093 }; 1094 1095 pinctrl_lpuart2: lpuart2grp { 1096 fsl,pins = < 1097 IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 1098 IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 1099 >; 1100 }; 1101 1102 pinctrl_lpuart3: lpuart3grp { 1103 fsl,pins = < 1104 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 1105 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 1106 >; 1107 }; 1108 1109 pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { 1110 fsl,pins = < 1111 IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c 1112 IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c 1113 >; 1114 }; 1115 1116 pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { 1117 fsl,pins = < 1118 IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c 1119 IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c 1120 >; 1121 }; 1122 1123 pinctrl_mipi_csi0: mipi-csi0grp { 1124 fsl,pins = < 1125 IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 1126 IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 1127 IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 1128 >; 1129 }; 1130 1131 pinctrl_mipi_csi1: mipi-csi1grp { 1132 fsl,pins = < 1133 IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 1134 IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 1135 IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 1136 >; 1137 }; 1138 1139 pinctrl_pciea: pcieagrp { 1140 fsl,pins = < 1141 IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 1142 IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 1143 IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 1144 >; 1145 }; 1146 1147 pinctrl_pciea_reg: pcieareggrp { 1148 fsl,pins = < 1149 IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000021 1150 >; 1151 }; 1152 1153 pinctrl_pcieb: pciebgrp { 1154 fsl,pins = < 1155 IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021 1156 IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 1157 IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 1158 >; 1159 }; 1160 1161 pinctrl_pwm_lvds0: pwmlvds0grp { 1162 fsl,pins = < 1163 IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 1164 >; 1165 }; 1166 1167 pinctrl_pwm_lvds1: pwmlvds1grp { 1168 fsl,pins = < 1169 IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 1170 >; 1171 }; 1172 1173 pinctrl_sai0: sai0grp { 1174 fsl,pins = < 1175 IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c 1176 IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c 1177 IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c 1178 IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c 1179 >; 1180 }; 1181 1182 pinctrl_sai1: sai1grp { 1183 fsl,pins = < 1184 IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 1185 IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 1186 IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 1187 IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 1188 >; 1189 }; 1190 1191 pinctrl_typec: typecgrp { 1192 fsl,pins = < 1193 IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 1194 >; 1195 }; 1196 1197 pinctrl_typec_mux: typecmuxgrp { 1198 fsl,pins = < 1199 IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 1200 IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 1201 >; 1202 }; 1203 1204 pinctrl_usdhc1: usdhc1grp { 1205 fsl,pins = < 1206 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 1207 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 1208 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 1209 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 1210 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 1211 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 1212 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 1213 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 1214 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 1215 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 1216 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 1217 >; 1218 }; 1219 1220 pinctrl_usdhc2: usdhc2grp { 1221 fsl,pins = < 1222 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 1223 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 1224 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 1225 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 1226 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 1227 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 1228 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 1229 >; 1230 }; 1231}; 1232