1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/usb/pd.h> 10#include "imx8qm.dtsi" 11 12/ { 13 model = "Freescale i.MX8QM MEK"; 14 compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; 15 16 chosen { 17 stdout-path = &lpuart0; 18 }; 19 20 cpus { 21 /delete-node/ cpu-map; 22 /delete-node/ cpu@100; 23 /delete-node/ cpu@101; 24 }; 25 26 thermal-zones { 27 /delete-node/ cpu1-thermal; 28 }; 29 30 memory@80000000 { 31 device_type = "memory"; 32 reg = <0x00000000 0x80000000 0 0x40000000>; 33 }; 34 35 reserved-memory { 36 #address-cells = <2>; 37 #size-cells = <2>; 38 ranges; 39 40 vdev0vring0: memory@90000000 { 41 reg = <0 0x90000000 0 0x8000>; 42 no-map; 43 }; 44 45 vdev0vring1: memory@90008000 { 46 reg = <0 0x90008000 0 0x8000>; 47 no-map; 48 }; 49 50 vdev1vring0: memory@90010000 { 51 reg = <0 0x90010000 0 0x8000>; 52 no-map; 53 }; 54 55 vdev1vring1: memory@90018000 { 56 reg = <0 0x90018000 0 0x8000>; 57 no-map; 58 }; 59 60 rsc_table0: memory@900ff000 { 61 reg = <0 0x900ff000 0 0x1000>; 62 no-map; 63 }; 64 65 vdev2vring0: memory@90100000 { 66 reg = <0 0x90100000 0 0x8000>; 67 no-map; 68 }; 69 70 vdev2vring1: memory@90108000 { 71 reg = <0 0x90108000 0 0x8000>; 72 no-map; 73 }; 74 75 vdev3vring0: memory@90110000 { 76 reg = <0 0x90110000 0 0x8000>; 77 no-map; 78 }; 79 80 vdev3vring1: memory@90118000 { 81 reg = <0 0x90118000 0 0x8000>; 82 no-map; 83 }; 84 85 rsc_table1: memory@901ff000 { 86 reg = <0 0x901ff000 0 0x1000>; 87 no-map; 88 }; 89 90 vdevbuffer: memory@90400000 { 91 compatible = "shared-dma-pool"; 92 reg = <0 0x90400000 0 0x100000>; 93 no-map; 94 }; 95 }; 96 97 lvds_backlight0: backlight-lvds0 { 98 compatible = "pwm-backlight"; 99 pwms = <&qm_pwm_lvds0 0 100000 0>; 100 brightness-levels = <0 100>; 101 num-interpolated-steps = <100>; 102 default-brightness-level = <80>; 103 }; 104 105 lvds_backlight1: backlight-lvds1 { 106 compatible = "pwm-backlight"; 107 pwms = <&pwm_lvds1 0 100000 0>; 108 brightness-levels = <0 100>; 109 num-interpolated-steps = <100>; 110 default-brightness-level = <80>; 111 }; 112 113 mux-controller { 114 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_typec_mux>; 117 select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; 118 enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 119 orientation-switch; 120 121 port { 122 usb3_data_ss: endpoint { 123 remote-endpoint = <&typec_con_ss>; 124 }; 125 }; 126 }; 127 128 reg_usdhc2_vmmc: usdhc2-vmmc { 129 compatible = "regulator-fixed"; 130 regulator-name = "SD1_SPWR"; 131 regulator-min-microvolt = <3000000>; 132 regulator-max-microvolt = <3000000>; 133 gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; 134 enable-active-high; 135 }; 136 137 reg_fec2_supply: regulator-fec2-nvcc { 138 compatible = "regulator-fixed"; 139 regulator-name = "fec2_nvcc"; 140 regulator-min-microvolt = <1800000>; 141 regulator-max-microvolt = <1800000>; 142 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; 143 enable-active-high; 144 }; 145 146 reg_can01_en: regulator-can01-gen { 147 compatible = "regulator-fixed"; 148 regulator-name = "can01-en"; 149 regulator-min-microvolt = <3300000>; 150 regulator-max-microvolt = <3300000>; 151 gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; 152 enable-active-high; 153 }; 154 155 reg_can2_en: regulator-can2-gen { 156 compatible = "regulator-fixed"; 157 regulator-name = "can2-en"; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; 161 enable-active-high; 162 }; 163 164 reg_can01_stby: regulator-can01-stby { 165 compatible = "regulator-fixed"; 166 regulator-name = "can01-stby"; 167 regulator-min-microvolt = <3300000>; 168 regulator-max-microvolt = <3300000>; 169 gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; 170 enable-active-high; 171 vin-supply = <®_can01_en>; 172 }; 173 174 reg_can2_stby: regulator-can2-stby { 175 compatible = "regulator-fixed"; 176 regulator-name = "can2-stby"; 177 regulator-min-microvolt = <3300000>; 178 regulator-max-microvolt = <3300000>; 179 gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; 180 enable-active-high; 181 vin-supply = <®_can2_en>; 182 }; 183 184 reg_vref_1v8: regulator-adc-vref { 185 compatible = "regulator-fixed"; 186 regulator-name = "vref_1v8"; 187 regulator-min-microvolt = <1800000>; 188 regulator-max-microvolt = <1800000>; 189 }; 190 191 bt_sco_codec: audio-codec-bt { 192 compatible = "linux,bt-sco"; 193 #sound-dai-cells = <1>; 194 }; 195 196 sound-bt-sco { 197 compatible = "simple-audio-card"; 198 simple-audio-card,name = "bt-sco-audio"; 199 simple-audio-card,format = "dsp_a"; 200 simple-audio-card,bitclock-inversion; 201 simple-audio-card,frame-master = <&btcpu>; 202 simple-audio-card,bitclock-master = <&btcpu>; 203 204 btcpu: simple-audio-card,cpu { 205 sound-dai = <&sai0>; 206 dai-tdm-slot-num = <2>; 207 dai-tdm-slot-width = <16>; 208 }; 209 210 simple-audio-card,codec { 211 sound-dai = <&bt_sco_codec 1>; 212 }; 213 }; 214 215 sound-wm8960 { 216 compatible = "fsl,imx-audio-wm8960"; 217 model = "wm8960-audio"; 218 audio-cpu = <&sai1>; 219 audio-codec = <&wm8960>; 220 hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; 221 audio-routing = "Headphone Jack", "HP_L", 222 "Headphone Jack", "HP_R", 223 "Ext Spk", "SPK_LP", 224 "Ext Spk", "SPK_LN", 225 "Ext Spk", "SPK_RP", 226 "Ext Spk", "SPK_RN", 227 "LINPUT1", "Mic Jack", 228 "Mic Jack", "MICB"; 229 }; 230 231 imx8qm-cm4-0 { 232 compatible = "fsl,imx8qm-cm4"; 233 clocks = <&clk_dummy>; 234 mbox-names = "tx", "rx", "rxdb"; 235 mboxes = <&lsio_mu5 0 1 236 &lsio_mu5 1 1 237 &lsio_mu5 3 1>; 238 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 239 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>; 240 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; 241 242 fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 243 fsl,entry-address = <0x34fe0000>; 244 }; 245 246 imx8qm-cm4-1 { 247 compatible = "fsl,imx8qm-cm4"; 248 clocks = <&clk_dummy>; 249 mbox-names = "tx", "rx", "rxdb"; 250 mboxes = <&lsio_mu6 0 1 251 &lsio_mu6 1 1 252 &lsio_mu6 3 1>; 253 memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>, 254 <&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>; 255 power-domains = <&pd IMX_SC_R_M4_1_PID0>, <&pd IMX_SC_R_M4_1_MU_1A>; 256 257 fsl,resource-id = <IMX_SC_R_M4_1_PID0>; 258 fsl,entry-address = <0x38fe0000>; 259 }; 260 261}; 262 263&adc0 { 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_adc0>; 266 vref-supply = <®_vref_1v8>; 267 status = "okay"; 268}; 269 270&amix { 271 status = "okay"; 272}; 273 274&asrc0 { 275 fsl,asrc-rate = <48000>; 276 status = "okay"; 277}; 278 279&cm41_i2c { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 clock-frequency = <100000>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pinctrl_cm41_i2c>; 285 status = "okay"; 286 287 pca6416: gpio@20 { 288 compatible = "ti,tca6416"; 289 reg = <0x20>; 290 gpio-controller; 291 #gpio-cells = <2>; 292 }; 293}; 294 295&cm41_intmux { 296 status = "okay"; 297}; 298 299&i2c0 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 clock-frequency = <100000>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_i2c0>; 305 status = "okay"; 306 307 accelerometer@19 { 308 compatible = "st,lsm303agr-accel"; 309 reg = <0x19>; 310 }; 311 312 gyrometer@20 { 313 compatible = "nxp,fxas21002c"; 314 reg = <0x20>; 315 }; 316 317 light-sensor@44 { 318 compatible = "isil,isl29023"; 319 reg = <0x44>; 320 interrupt-parent = <&lsio_gpio4>; 321 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 322 }; 323 324 pressure-sensor@60 { 325 compatible = "fsl,mpl3115"; 326 reg = <0x60>; 327 }; 328 329 max7322: gpio@68 { 330 compatible = "maxim,max7322"; 331 reg = <0x68>; 332 gpio-controller; 333 #gpio-cells = <2>; 334 }; 335 336 gyrometer@69 { 337 compatible = "st,l3g4200d-gyro"; 338 reg = <0x69>; 339 }; 340 341 ptn5110: tcpc@51 { 342 compatible = "nxp,ptn5110", "tcpci"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_typec>; 345 reg = <0x51>; 346 interrupt-parent = <&lsio_gpio4>; 347 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 348 status = "okay"; 349 350 usb_con1: connector { 351 compatible = "usb-c-connector"; 352 label = "USB-C"; 353 power-role = "source"; 354 data-role = "dual"; 355 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 356 357 ports { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 361 port@0 { 362 reg = <0>; 363 364 typec_dr_sw: endpoint { 365 remote-endpoint = <&usb3_drd_sw>; 366 }; 367 }; 368 369 port@1 { 370 reg = <1>; 371 typec_con_ss: endpoint { 372 remote-endpoint = <&usb3_data_ss>; 373 }; 374 }; 375 }; 376 }; 377 }; 378}; 379 380&i2c1 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clock-frequency = <100000>; 384 pinctrl-names = "default", "gpio"; 385 pinctrl-0 = <&pinctrl_i2c1>; 386 pinctrl-1 = <&pinctrl_i2c1_gpio>; 387 scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; 388 sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; 389 status = "okay"; 390 391 wm8960: audio-codec@1a { 392 compatible = "wlf,wm8960"; 393 reg = <0x1a>; 394 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 395 clock-names = "mclk"; 396 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 397 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 398 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 399 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 400 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 401 wlf,shared-lrclk; 402 wlf,hp-cfg = <2 2 3>; 403 wlf,gpio-cfg = <1 3>; 404 }; 405}; 406 407&i2c1_lvds0 { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; 410 clock-frequency = <100000>; 411 status = "okay"; 412}; 413 414&i2c1_lvds1 { 415 pinctrl-names = "default"; 416 pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; 417 clock-frequency = <100000>; 418 status = "okay"; 419}; 420 421&i2c0_mipi0 { 422 pinctrl-names = "default"; 423 pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; 424 clock-frequency = <100000>; 425 status = "okay"; 426}; 427 428&i2c0_mipi1 { 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; 431 clock-frequency = <100000>; 432 status = "okay"; 433}; 434 435&flexcan1 { 436 pinctrl-names = "default"; 437 pinctrl-0 = <&pinctrl_flexcan1>; 438 xceiver-supply = <®_can01_stby>; 439 status = "okay"; 440}; 441 442&flexcan2 { 443 pinctrl-names = "default"; 444 pinctrl-0 = <&pinctrl_flexcan2>; 445 xceiver-supply = <®_can01_stby>; 446 status = "okay"; 447}; 448 449&flexcan3 { 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_flexcan3>; 452 xceiver-supply = <®_can2_stby>; 453 status = "okay"; 454}; 455 456&lpuart0 { 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pinctrl_lpuart0>; 459 status = "okay"; 460}; 461 462&lpuart2 { 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pinctrl_lpuart2>; 465 status = "okay"; 466}; 467 468&lpuart3 { 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_lpuart3>; 471 status = "okay"; 472}; 473 474&lpspi2 { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; 479 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; 480 status = "okay"; 481}; 482 483&lsio_mu5 { 484 status = "okay"; 485}; 486 487&lsio_mu6 { 488 status = "okay"; 489}; 490 491&flexspi0 { 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pinctrl_flexspi0>; 494 status = "okay"; 495 496 flash0: flash@0 { 497 reg = <0>; 498 #address-cells = <1>; 499 #size-cells = <1>; 500 compatible = "jedec,spi-nor"; 501 spi-max-frequency = <133000000>; 502 spi-tx-bus-width = <8>; 503 spi-rx-bus-width = <8>; 504 }; 505}; 506 507&fec1 { 508 pinctrl-names = "default"; 509 pinctrl-0 = <&pinctrl_fec1>; 510 phy-mode = "rgmii-id"; 511 phy-handle = <ðphy0>; 512 fsl,magic-packet; 513 status = "okay"; 514 515 mdio { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 519 ethphy0: ethernet-phy@0 { 520 compatible = "ethernet-phy-ieee802.3-c22"; 521 reg = <0>; 522 }; 523 524 ethphy1: ethernet-phy@1 { 525 compatible = "ethernet-phy-ieee802.3-c22"; 526 reg = <1>; 527 }; 528 }; 529}; 530 531&fec2 { 532 pinctrl-names = "default"; 533 pinctrl-0 = <&pinctrl_fec2>; 534 phy-mode = "rgmii-txid"; 535 phy-handle = <ðphy1>; 536 phy-supply = <®_fec2_supply>; 537 nvmem-cells = <&fec_mac1>; 538 nvmem-cell-names = "mac-address"; 539 rx-internal-delay-ps = <2000>; 540 fsl,magic-packet; 541 status = "okay"; 542}; 543 544&qm_pwm_lvds0 { 545 pinctrl-names = "default"; 546 pinctrl-0 = <&pinctrl_pwm_lvds0>; 547 status = "okay"; 548}; 549 550&pwm_lvds1 { 551 pinctrl-names = "default"; 552 pinctrl-0 = <&pinctrl_pwm_lvds1>; 553 status = "okay"; 554}; 555 556&usdhc1 { 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pinctrl_usdhc1>; 559 bus-width = <8>; 560 no-sd; 561 no-sdio; 562 non-removable; 563 status = "okay"; 564}; 565 566&usdhc2 { 567 pinctrl-names = "default"; 568 pinctrl-0 = <&pinctrl_usdhc2>; 569 bus-width = <4>; 570 vmmc-supply = <®_usdhc2_vmmc>; 571 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; 572 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; 573 status = "okay"; 574}; 575 576&usb3_phy { 577 status = "okay"; 578}; 579 580&usbotg3 { 581 status = "okay"; 582}; 583 584&usbotg3_cdns3 { 585 dr_mode = "otg"; 586 usb-role-switch; 587 status = "okay"; 588 589 port { 590 usb3_drd_sw: endpoint { 591 remote-endpoint = <&typec_dr_sw>; 592 }; 593 }; 594}; 595 596&sai0 { 597 #sound-dai-cells = <0>; 598 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 599 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 600 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 601 <&sai0_lpcg IMX_LPCG_CLK_4>; 602 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&pinctrl_sai0>; 605 status = "okay"; 606}; 607 608&sai1 { 609 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 610 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 611 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 612 <&sai1_lpcg IMX_LPCG_CLK_4>; 613 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&pinctrl_sai1>; 616 status = "okay"; 617}; 618 619&sai6 { 620 assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, 621 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 622 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 623 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 624 <&sai6_lpcg IMX_LPCG_CLK_4>; 625 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 626 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 627 fsl,sai-asynchronous; 628 status = "okay"; 629}; 630 631&sai7 { 632 assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, 633 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 634 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 635 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 636 <&sai7_lpcg IMX_LPCG_CLK_4>; 637 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 638 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 639 fsl,sai-asynchronous; 640 status = "okay"; 641}; 642 643&iomuxc { 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pinctrl_hog>; 646 647 pinctrl_hog: hoggrp { 648 fsl,pins = < 649 IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c 650 IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c 651 >; 652 }; 653 654 pinctrl_i2c0: i2c0grp { 655 fsl,pins = < 656 IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 657 IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 658 >; 659 }; 660 661 pinctrl_i2c1: i2c1grp { 662 fsl,pins = < 663 IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c 664 IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c 665 >; 666 }; 667 668 pinctrl_i2c1_gpio: i2c1gpio-grp { 669 fsl,pins = < 670 IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c 671 IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c 672 >; 673 }; 674 675 pinctrl_adc0: adc0grp { 676 fsl,pins = < 677 IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 678 >; 679 }; 680 681 pinctrl_cm41_i2c: cm41i2cgrp { 682 fsl,pins = < 683 IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c 684 IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c 685 >; 686 }; 687 688 pinctrl_fec1: fec1grp { 689 fsl,pins = < 690 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 691 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 692 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 693 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 694 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 695 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 696 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 697 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 698 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 699 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 700 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 701 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 702 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 703 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 704 >; 705 }; 706 707 pinctrl_lpspi2: lpspi2grp { 708 fsl,pins = < 709 IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040 710 IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040 711 IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040 712 >; 713 }; 714 715 pinctrl_lpspi2_cs: lpspi2csgrp { 716 fsl,pins = < 717 IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 718 >; 719 }; 720 721 pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { 722 fsl,pins = < 723 IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 724 IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 725 IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 726 >; 727 }; 728 729 pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { 730 fsl,pins = < 731 IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 732 IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 733 IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 734 >; 735 }; 736 737 pinctrl_flexspi0: flexspi0grp { 738 fsl,pins = < 739 IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 740 IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 741 IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 742 IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 743 IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 744 IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 745 IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 746 IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 747 IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 748 IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 749 IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 750 IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 751 IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 752 IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 753 IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 754 IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 755 >; 756 }; 757 758 pinctrl_fec2: fec2grp { 759 fsl,pins = < 760 IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 761 IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 762 IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 763 IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 764 IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 765 IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 766 IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 767 IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 768 IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 769 IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 770 IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 771 IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 772 IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 773 >; 774 }; 775 776 pinctrl_flexcan1: flexcan0grp { 777 fsl,pins = < 778 IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 779 IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 780 >; 781 }; 782 783 pinctrl_flexcan2: flexcan1grp { 784 fsl,pins = < 785 IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 786 IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 787 >; 788 }; 789 790 pinctrl_flexcan3: flexcan3grp { 791 fsl,pins = < 792 IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 793 IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 794 >; 795 }; 796 797 pinctrl_lpuart0: lpuart0grp { 798 fsl,pins = < 799 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 800 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 801 >; 802 }; 803 804 pinctrl_lpuart2: lpuart2grp { 805 fsl,pins = < 806 IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 807 IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 808 >; 809 }; 810 811 pinctrl_lpuart3: lpuart3grp { 812 fsl,pins = < 813 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 814 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 815 >; 816 }; 817 818 pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { 819 fsl,pins = < 820 IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c 821 IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c 822 >; 823 }; 824 825 pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { 826 fsl,pins = < 827 IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c 828 IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c 829 >; 830 }; 831 832 pinctrl_pwm_lvds0: pwmlvds0grp { 833 fsl,pins = < 834 IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 835 >; 836 }; 837 838 pinctrl_pwm_lvds1: pwmlvds1grp { 839 fsl,pins = < 840 IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 841 >; 842 }; 843 844 pinctrl_sai0: sai0grp { 845 fsl,pins = < 846 IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c 847 IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c 848 IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c 849 IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c 850 >; 851 }; 852 853 pinctrl_sai1: sai1grp { 854 fsl,pins = < 855 IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 856 IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 857 IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 858 IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 859 >; 860 }; 861 862 pinctrl_typec: typecgrp { 863 fsl,pins = < 864 IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 865 >; 866 }; 867 868 pinctrl_typec_mux: typecmuxgrp { 869 fsl,pins = < 870 IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 871 IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 872 >; 873 }; 874 875 pinctrl_usdhc1: usdhc1grp { 876 fsl,pins = < 877 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 878 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 879 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 880 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 881 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 882 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 883 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 884 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 885 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 886 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 887 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 888 >; 889 }; 890 891 pinctrl_usdhc2: usdhc2grp { 892 fsl,pins = < 893 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 894 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 895 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 896 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 897 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 898 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 899 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 900 >; 901 }; 902}; 903