1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7/dts-v1/; 8 9#include "imx8qm.dtsi" 10 11/ { 12 model = "Freescale i.MX8QM MEK"; 13 compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; 14 15 chosen { 16 stdout-path = &lpuart0; 17 }; 18 19 cpus { 20 /delete-node/ cpu-map; 21 /delete-node/ cpu@100; 22 /delete-node/ cpu@101; 23 }; 24 25 thermal-zones { 26 /delete-node/ cpu1-thermal; 27 }; 28 29 memory@80000000 { 30 device_type = "memory"; 31 reg = <0x00000000 0x80000000 0 0x40000000>; 32 }; 33 34 reg_usdhc2_vmmc: usdhc2-vmmc { 35 compatible = "regulator-fixed"; 36 regulator-name = "SD1_SPWR"; 37 regulator-min-microvolt = <3000000>; 38 regulator-max-microvolt = <3000000>; 39 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 40 enable-active-high; 41 }; 42}; 43 44&i2c1 { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 clock-frequency = <100000>; 48 pinctrl-names = "default", "gpio"; 49 pinctrl-0 = <&pinctrl_i2c1>; 50 pinctrl-1 = <&pinctrl_i2c1_gpio>; 51 scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; 52 sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; 53 status = "okay"; 54}; 55 56&lpuart0 { 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_lpuart0>; 59 status = "okay"; 60}; 61 62&lpuart2 { 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_lpuart2>; 65 status = "okay"; 66}; 67 68&lpuart3 { 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_lpuart3>; 71 status = "okay"; 72}; 73 74&fec1 { 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_fec1>; 77 phy-mode = "rgmii-id"; 78 phy-handle = <ðphy0>; 79 fsl,magic-packet; 80 status = "okay"; 81 82 mdio { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 ethphy0: ethernet-phy@0 { 87 compatible = "ethernet-phy-ieee802.3-c22"; 88 reg = <0>; 89 }; 90 91 ethphy1: ethernet-phy@1 { 92 compatible = "ethernet-phy-ieee802.3-c22"; 93 reg = <1>; 94 }; 95 }; 96}; 97 98&usdhc1 { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_usdhc1>; 101 bus-width = <8>; 102 no-sd; 103 no-sdio; 104 non-removable; 105 status = "okay"; 106}; 107 108&usdhc2 { 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_usdhc2>; 111 bus-width = <4>; 112 vmmc-supply = <®_usdhc2_vmmc>; 113 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; 114 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; 115 status = "okay"; 116}; 117 118&iomuxc { 119 pinctrl_i2c1: i2c1grp { 120 fsl,pins = < 121 IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c 122 IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c 123 >; 124 }; 125 126 pinctrl_i2c1_gpio: i2c1gpio-grp { 127 fsl,pins = < 128 IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c 129 IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c 130 >; 131 }; 132 133 pinctrl_fec1: fec1grp { 134 fsl,pins = < 135 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 136 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 137 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 138 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 139 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 140 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 141 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 142 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 143 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 144 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 145 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 146 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 147 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 148 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 149 >; 150 }; 151 152 pinctrl_lpuart0: lpuart0grp { 153 fsl,pins = < 154 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 155 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 156 >; 157 }; 158 159 pinctrl_lpuart2: lpuart2grp { 160 fsl,pins = < 161 IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 162 IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 163 >; 164 }; 165 166 pinctrl_lpuart3: lpuart3grp { 167 fsl,pins = < 168 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 169 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 170 >; 171 }; 172 173 pinctrl_usdhc1: usdhc1grp { 174 fsl,pins = < 175 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 176 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 177 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 178 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 179 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 180 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 181 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 182 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 183 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 184 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 185 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 186 >; 187 }; 188 189 pinctrl_usdhc2: usdhc2grp { 190 fsl,pins = < 191 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 192 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 193 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 194 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 195 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 196 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 197 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 198 >; 199 }; 200}; 201