xref: /linux/arch/arm64/boot/dts/freescale/imx8qm-mek.dts (revision 90d32e92011eaae8e70a9169b4e7acf4ca8f9d3a) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7/dts-v1/;
8
9#include "imx8qm.dtsi"
10
11/ {
12	model = "Freescale i.MX8QM MEK";
13	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
14
15	chosen {
16		stdout-path = &lpuart0;
17	};
18
19	cpus {
20		/delete-node/ cpu-map;
21		/delete-node/ cpu@100;
22		/delete-node/ cpu@101;
23	};
24
25	thermal-zones {
26		/delete-node/ cpu1-thermal;
27	};
28
29	memory@80000000 {
30		device_type = "memory";
31		reg = <0x00000000 0x80000000 0 0x40000000>;
32	};
33
34	reg_usdhc2_vmmc: usdhc2-vmmc {
35		compatible = "regulator-fixed";
36		regulator-name = "SD1_SPWR";
37		regulator-min-microvolt = <3000000>;
38		regulator-max-microvolt = <3000000>;
39		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
40		enable-active-high;
41	};
42
43	reg_vref_1v8: regulator-adc-vref {
44		compatible = "regulator-fixed";
45		regulator-name = "vref_1v8";
46		regulator-min-microvolt = <1800000>;
47		regulator-max-microvolt = <1800000>;
48	};
49};
50
51&adc0 {
52	pinctrl-names = "default";
53	pinctrl-0 = <&pinctrl_adc0>;
54	vref-supply = <&reg_vref_1v8>;
55	status = "okay";
56};
57
58&i2c1 {
59	#address-cells = <1>;
60	#size-cells = <0>;
61	clock-frequency = <100000>;
62	pinctrl-names = "default", "gpio";
63	pinctrl-0 = <&pinctrl_i2c1>;
64	pinctrl-1 = <&pinctrl_i2c1_gpio>;
65	scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
66	sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
67	status = "okay";
68};
69
70&lpuart0 {
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_lpuart0>;
73	status = "okay";
74};
75
76&lpuart2 {
77	pinctrl-names = "default";
78	pinctrl-0 = <&pinctrl_lpuart2>;
79	status = "okay";
80};
81
82&lpuart3 {
83	pinctrl-names = "default";
84	pinctrl-0 = <&pinctrl_lpuart3>;
85	status = "okay";
86};
87
88&lpspi2 {
89	#address-cells = <1>;
90	#size-cells = <0>;
91	pinctrl-names = "default";
92	pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
93	cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
94	status = "okay";
95
96	spidev0: spi@0 {
97		reg = <0>;
98		compatible = "rohm,dh2228fv";
99		spi-max-frequency = <30000000>;
100	};
101};
102
103&flexspi0 {
104	pinctrl-names = "default";
105	pinctrl-0 = <&pinctrl_flexspi0>;
106	status = "okay";
107
108	flash0: flash@0 {
109		reg = <0>;
110		#address-cells = <1>;
111		#size-cells = <1>;
112		compatible = "jedec,spi-nor";
113		spi-max-frequency = <133000000>;
114		spi-tx-bus-width = <8>;
115		spi-rx-bus-width = <8>;
116	};
117};
118
119&fec1 {
120	pinctrl-names = "default";
121	pinctrl-0 = <&pinctrl_fec1>;
122	phy-mode = "rgmii-id";
123	phy-handle = <&ethphy0>;
124	fsl,magic-packet;
125	status = "okay";
126
127	mdio {
128		#address-cells = <1>;
129		#size-cells = <0>;
130
131		ethphy0: ethernet-phy@0 {
132			compatible = "ethernet-phy-ieee802.3-c22";
133			reg = <0>;
134		};
135
136		ethphy1: ethernet-phy@1 {
137			compatible = "ethernet-phy-ieee802.3-c22";
138			reg = <1>;
139		};
140	};
141};
142
143&usdhc1 {
144	pinctrl-names = "default";
145	pinctrl-0 = <&pinctrl_usdhc1>;
146	bus-width = <8>;
147	no-sd;
148	no-sdio;
149	non-removable;
150	status = "okay";
151};
152
153&usdhc2 {
154	pinctrl-names = "default";
155	pinctrl-0 = <&pinctrl_usdhc2>;
156	bus-width = <4>;
157	vmmc-supply = <&reg_usdhc2_vmmc>;
158	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
159	wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
160	status = "okay";
161};
162
163&iomuxc {
164	pinctrl_i2c1: i2c1grp {
165		fsl,pins = <
166			IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
167			IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
168		>;
169	};
170
171	pinctrl_i2c1_gpio: i2c1gpio-grp {
172		fsl,pins = <
173			IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14		0xc600004c
174			IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15	0xc600004c
175		>;
176	};
177
178	pinctrl_adc0: adc0grp {
179		fsl,pins = <
180			IMX8QM_ADC_IN0_DMA_ADC0_IN0				0xc0000060
181		>;
182	};
183
184	pinctrl_fec1: fec1grp {
185		fsl,pins = <
186			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020
187			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
188			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
189			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
190			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
191			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
192			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
193			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
194			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
195			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
196			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
197			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
198			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
199			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
200		>;
201	};
202
203	pinctrl_lpspi2: lpspi2grp {
204		fsl,pins = <
205			IMX8QM_SPI2_SCK_DMA_SPI2_SCK		0x06000040
206			IMX8QM_SPI2_SDO_DMA_SPI2_SDO		0x06000040
207			IMX8QM_SPI2_SDI_DMA_SPI2_SDI		0x06000040
208		>;
209	};
210
211	pinctrl_lpspi2_cs: lpspi2csgrp {
212		fsl,pins = <
213			IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10		0x21
214		>;
215	};
216
217	pinctrl_flexspi0: flexspi0grp {
218		fsl,pins = <
219			IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
220			IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
221			IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
222			IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
223			IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
224			IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
225			IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B     0x06000021
226			IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
227			IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
228			IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
229			IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
230			IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
231			IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
232			IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
233			IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
234			IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B     0x06000021
235		>;
236	};
237
238	pinctrl_lpuart0: lpuart0grp {
239		fsl,pins = <
240			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
241			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020
242		>;
243	};
244
245	pinctrl_lpuart2: lpuart2grp {
246		fsl,pins = <
247			IMX8QM_UART0_RTS_B_DMA_UART2_RX				0x06000020
248			IMX8QM_UART0_CTS_B_DMA_UART2_TX				0x06000020
249		>;
250	};
251
252	pinctrl_lpuart3: lpuart3grp {
253		fsl,pins = <
254			IMX8QM_M41_GPIO0_00_DMA_UART3_RX			0x06000020
255			IMX8QM_M41_GPIO0_01_DMA_UART3_TX			0x06000020
256		>;
257	};
258
259	pinctrl_usdhc1: usdhc1grp {
260		fsl,pins = <
261			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
262			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
263			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
264			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
265			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
266			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
267			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
268			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
269			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
270			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
271			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
272		>;
273	};
274
275	pinctrl_usdhc2: usdhc2grp {
276		fsl,pins = <
277			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
278			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
279			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
280			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
281			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
282			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
283			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
284		>;
285	};
286};
287