1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/usb/pd.h> 10#include "imx8qm.dtsi" 11 12/ { 13 model = "Freescale i.MX8QM MEK"; 14 compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; 15 16 chosen { 17 stdout-path = &lpuart0; 18 }; 19 20 cpus { 21 /delete-node/ cpu-map; 22 /delete-node/ cpu@100; 23 /delete-node/ cpu@101; 24 }; 25 26 thermal-zones { 27 /delete-node/ cpu1-thermal; 28 }; 29 30 memory@80000000 { 31 device_type = "memory"; 32 reg = <0x00000000 0x80000000 0 0x40000000>; 33 }; 34 35 reserved-memory { 36 #address-cells = <2>; 37 #size-cells = <2>; 38 ranges; 39 40 vdev0vring0: memory@90000000 { 41 reg = <0 0x90000000 0 0x8000>; 42 no-map; 43 }; 44 45 vdev0vring1: memory@90008000 { 46 reg = <0 0x90008000 0 0x8000>; 47 no-map; 48 }; 49 50 vdev1vring0: memory@90010000 { 51 reg = <0 0x90010000 0 0x8000>; 52 no-map; 53 }; 54 55 vdev1vring1: memory@90018000 { 56 reg = <0 0x90018000 0 0x8000>; 57 no-map; 58 }; 59 60 rsc_table0: memory@900ff000 { 61 reg = <0 0x900ff000 0 0x1000>; 62 no-map; 63 }; 64 65 vdev2vring0: memory@90100000 { 66 reg = <0 0x90100000 0 0x8000>; 67 no-map; 68 }; 69 70 vdev2vring1: memory@90108000 { 71 reg = <0 0x90108000 0 0x8000>; 72 no-map; 73 }; 74 75 vdev3vring0: memory@90110000 { 76 reg = <0 0x90110000 0 0x8000>; 77 no-map; 78 }; 79 80 vdev3vring1: memory@90118000 { 81 reg = <0 0x90118000 0 0x8000>; 82 no-map; 83 }; 84 85 rsc_table1: memory@901ff000 { 86 reg = <0 0x901ff000 0 0x1000>; 87 no-map; 88 }; 89 90 vdevbuffer: memory@90400000 { 91 compatible = "shared-dma-pool"; 92 reg = <0 0x90400000 0 0x100000>; 93 no-map; 94 }; 95 96 dsp_reserved: memory@92400000 { 97 reg = <0 0x92400000 0 0x1000000>; 98 no-map; 99 }; 100 101 dsp_vdev0vring0: memory@942f0000 { 102 reg = <0 0x942f0000 0 0x8000>; 103 no-map; 104 }; 105 106 dsp_vdev0vring1: memory@942f8000 { 107 reg = <0 0x942f8000 0 0x8000>; 108 no-map; 109 }; 110 111 dsp_vdev0buffer: memory@94300000 { 112 compatible = "shared-dma-pool"; 113 reg = <0 0x94300000 0 0x100000>; 114 no-map; 115 }; 116 }; 117 118 lvds_backlight0: backlight-lvds0 { 119 compatible = "pwm-backlight"; 120 pwms = <&qm_pwm_lvds0 0 100000 0>; 121 brightness-levels = <0 100>; 122 num-interpolated-steps = <100>; 123 default-brightness-level = <80>; 124 }; 125 126 lvds_backlight1: backlight-lvds1 { 127 compatible = "pwm-backlight"; 128 pwms = <&pwm_lvds1 0 100000 0>; 129 brightness-levels = <0 100>; 130 num-interpolated-steps = <100>; 131 default-brightness-level = <80>; 132 }; 133 134 mux-controller { 135 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_typec_mux>; 138 select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; 139 enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 140 orientation-switch; 141 142 port { 143 usb3_data_ss: endpoint { 144 remote-endpoint = <&typec_con_ss>; 145 }; 146 }; 147 }; 148 149 reg_usdhc2_vmmc: usdhc2-vmmc { 150 compatible = "regulator-fixed"; 151 regulator-name = "SD1_SPWR"; 152 regulator-min-microvolt = <3000000>; 153 regulator-max-microvolt = <3000000>; 154 gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; 155 enable-active-high; 156 }; 157 158 reg_fec2_supply: regulator-fec2-nvcc { 159 compatible = "regulator-fixed"; 160 regulator-name = "fec2_nvcc"; 161 regulator-min-microvolt = <1800000>; 162 regulator-max-microvolt = <1800000>; 163 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; 164 enable-active-high; 165 }; 166 167 reg_can01_en: regulator-can01-gen { 168 compatible = "regulator-fixed"; 169 regulator-name = "can01-en"; 170 regulator-min-microvolt = <3300000>; 171 regulator-max-microvolt = <3300000>; 172 gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; 173 enable-active-high; 174 }; 175 176 reg_can2_en: regulator-can2-gen { 177 compatible = "regulator-fixed"; 178 regulator-name = "can2-en"; 179 regulator-min-microvolt = <3300000>; 180 regulator-max-microvolt = <3300000>; 181 gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; 182 enable-active-high; 183 }; 184 185 reg_can01_stby: regulator-can01-stby { 186 compatible = "regulator-fixed"; 187 regulator-name = "can01-stby"; 188 regulator-min-microvolt = <3300000>; 189 regulator-max-microvolt = <3300000>; 190 gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; 191 enable-active-high; 192 vin-supply = <®_can01_en>; 193 }; 194 195 reg_can2_stby: regulator-can2-stby { 196 compatible = "regulator-fixed"; 197 regulator-name = "can2-stby"; 198 regulator-min-microvolt = <3300000>; 199 regulator-max-microvolt = <3300000>; 200 gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; 201 enable-active-high; 202 vin-supply = <®_can2_en>; 203 }; 204 205 reg_pciea: regulator-pcie { 206 compatible = "regulator-fixed"; 207 pinctrl-0 = <&pinctrl_pciea_reg>; 208 pinctrl-names = "default"; 209 regulator-max-microvolt = <3300000>; 210 regulator-min-microvolt = <3300000>; 211 regulator-name = "mpcie_3v3"; 212 gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; 213 enable-active-high; 214 }; 215 216 reg_vref_1v8: regulator-adc-vref { 217 compatible = "regulator-fixed"; 218 regulator-name = "vref_1v8"; 219 regulator-min-microvolt = <1800000>; 220 regulator-max-microvolt = <1800000>; 221 }; 222 223 bt_sco_codec: audio-codec-bt { 224 compatible = "linux,bt-sco"; 225 #sound-dai-cells = <1>; 226 }; 227 228 sound-bt-sco { 229 compatible = "simple-audio-card"; 230 simple-audio-card,name = "bt-sco-audio"; 231 simple-audio-card,format = "dsp_a"; 232 simple-audio-card,bitclock-inversion; 233 simple-audio-card,frame-master = <&btcpu>; 234 simple-audio-card,bitclock-master = <&btcpu>; 235 236 btcpu: simple-audio-card,cpu { 237 sound-dai = <&sai0>; 238 dai-tdm-slot-num = <2>; 239 dai-tdm-slot-width = <16>; 240 }; 241 242 simple-audio-card,codec { 243 sound-dai = <&bt_sco_codec 1>; 244 }; 245 }; 246 247 sound-wm8960 { 248 compatible = "fsl,imx-audio-wm8960"; 249 model = "wm8960-audio"; 250 audio-cpu = <&sai1>; 251 audio-codec = <&wm8960>; 252 hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; 253 audio-routing = "Headphone Jack", "HP_L", 254 "Headphone Jack", "HP_R", 255 "Ext Spk", "SPK_LP", 256 "Ext Spk", "SPK_LN", 257 "Ext Spk", "SPK_RP", 258 "Ext Spk", "SPK_RN", 259 "LINPUT1", "Mic Jack", 260 "Mic Jack", "MICB"; 261 }; 262 263 imx8qm-cm4-0 { 264 compatible = "fsl,imx8qm-cm4"; 265 clocks = <&clk_dummy>; 266 mbox-names = "tx", "rx", "rxdb"; 267 mboxes = <&lsio_mu5 0 1 268 &lsio_mu5 1 1 269 &lsio_mu5 3 1>; 270 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 271 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>; 272 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; 273 274 fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 275 fsl,entry-address = <0x34fe0000>; 276 }; 277 278 imx8qm-cm4-1 { 279 compatible = "fsl,imx8qm-cm4"; 280 clocks = <&clk_dummy>; 281 mbox-names = "tx", "rx", "rxdb"; 282 mboxes = <&lsio_mu6 0 1 283 &lsio_mu6 1 1 284 &lsio_mu6 3 1>; 285 memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>, 286 <&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>; 287 power-domains = <&pd IMX_SC_R_M4_1_PID0>, <&pd IMX_SC_R_M4_1_MU_1A>; 288 289 fsl,resource-id = <IMX_SC_R_M4_1_PID0>; 290 fsl,entry-address = <0x38fe0000>; 291 }; 292 293}; 294 295&adc0 { 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_adc0>; 298 vref-supply = <®_vref_1v8>; 299 status = "okay"; 300}; 301 302&amix { 303 status = "okay"; 304}; 305 306&asrc0 { 307 fsl,asrc-rate = <48000>; 308 status = "okay"; 309}; 310 311&cm41_i2c { 312 #address-cells = <1>; 313 #size-cells = <0>; 314 clock-frequency = <100000>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_cm41_i2c>; 317 status = "okay"; 318 319 pca6416: gpio@20 { 320 compatible = "ti,tca6416"; 321 reg = <0x20>; 322 gpio-controller; 323 #gpio-cells = <2>; 324 }; 325}; 326 327&cm41_intmux { 328 status = "okay"; 329}; 330 331&hsio_phy { 332 fsl,hsio-cfg = "pciea-pcieb-sata"; 333 fsl,refclk-pad-mode = "input"; 334 status = "okay"; 335}; 336 337&i2c0 { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 clock-frequency = <100000>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_i2c0>; 343 status = "okay"; 344 345 accelerometer@19 { 346 compatible = "st,lsm303agr-accel"; 347 reg = <0x19>; 348 }; 349 350 gyrometer@20 { 351 compatible = "nxp,fxas21002c"; 352 reg = <0x20>; 353 }; 354 355 light-sensor@44 { 356 compatible = "isil,isl29023"; 357 reg = <0x44>; 358 interrupt-parent = <&lsio_gpio4>; 359 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 360 }; 361 362 pressure-sensor@60 { 363 compatible = "fsl,mpl3115"; 364 reg = <0x60>; 365 }; 366 367 max7322: gpio@68 { 368 compatible = "maxim,max7322"; 369 reg = <0x68>; 370 gpio-controller; 371 #gpio-cells = <2>; 372 }; 373 374 gyrometer@69 { 375 compatible = "st,l3g4200d-gyro"; 376 reg = <0x69>; 377 }; 378 379 ptn5110: tcpc@51 { 380 compatible = "nxp,ptn5110", "tcpci"; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pinctrl_typec>; 383 reg = <0x51>; 384 interrupt-parent = <&lsio_gpio4>; 385 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 386 status = "okay"; 387 388 usb_con1: connector { 389 compatible = "usb-c-connector"; 390 label = "USB-C"; 391 power-role = "source"; 392 data-role = "dual"; 393 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 394 395 ports { 396 #address-cells = <1>; 397 #size-cells = <0>; 398 399 port@0 { 400 reg = <0>; 401 402 typec_dr_sw: endpoint { 403 remote-endpoint = <&usb3_drd_sw>; 404 }; 405 }; 406 407 port@1 { 408 reg = <1>; 409 typec_con_ss: endpoint { 410 remote-endpoint = <&usb3_data_ss>; 411 }; 412 }; 413 }; 414 }; 415 }; 416}; 417 418&i2c1 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 clock-frequency = <100000>; 422 pinctrl-names = "default", "gpio"; 423 pinctrl-0 = <&pinctrl_i2c1>; 424 pinctrl-1 = <&pinctrl_i2c1_gpio>; 425 scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; 426 sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; 427 status = "okay"; 428 429 wm8960: audio-codec@1a { 430 compatible = "wlf,wm8960"; 431 reg = <0x1a>; 432 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 433 clock-names = "mclk"; 434 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 435 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 436 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 437 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 438 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 439 wlf,shared-lrclk; 440 wlf,hp-cfg = <2 2 3>; 441 wlf,gpio-cfg = <1 3>; 442 }; 443}; 444 445&i2c1_lvds0 { 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; 448 clock-frequency = <100000>; 449 status = "okay"; 450}; 451 452&i2c1_lvds1 { 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; 455 clock-frequency = <100000>; 456 status = "okay"; 457}; 458 459&i2c0_mipi0 { 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; 462 clock-frequency = <100000>; 463 status = "okay"; 464}; 465 466&i2c0_mipi1 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; 469 clock-frequency = <100000>; 470 status = "okay"; 471}; 472 473&flexcan1 { 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pinctrl_flexcan1>; 476 xceiver-supply = <®_can01_stby>; 477 status = "okay"; 478}; 479 480&flexcan2 { 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_flexcan2>; 483 xceiver-supply = <®_can01_stby>; 484 status = "okay"; 485}; 486 487&flexcan3 { 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pinctrl_flexcan3>; 490 xceiver-supply = <®_can2_stby>; 491 status = "okay"; 492}; 493 494&lpuart0 { 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pinctrl_lpuart0>; 497 status = "okay"; 498}; 499 500&lpuart2 { 501 pinctrl-names = "default"; 502 pinctrl-0 = <&pinctrl_lpuart2>; 503 status = "okay"; 504}; 505 506&lpuart3 { 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pinctrl_lpuart3>; 509 status = "okay"; 510}; 511 512&lpspi2 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; 517 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; 518 status = "okay"; 519}; 520 521&lsio_mu5 { 522 status = "okay"; 523}; 524 525&lsio_mu6 { 526 status = "okay"; 527}; 528 529&flexspi0 { 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pinctrl_flexspi0>; 532 status = "okay"; 533 534 flash0: flash@0 { 535 reg = <0>; 536 #address-cells = <1>; 537 #size-cells = <1>; 538 compatible = "jedec,spi-nor"; 539 spi-max-frequency = <133000000>; 540 spi-tx-bus-width = <8>; 541 spi-rx-bus-width = <8>; 542 }; 543}; 544 545&fec1 { 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pinctrl_fec1>; 548 phy-mode = "rgmii-id"; 549 phy-handle = <ðphy0>; 550 fsl,magic-packet; 551 status = "okay"; 552 553 mdio { 554 #address-cells = <1>; 555 #size-cells = <0>; 556 557 ethphy0: ethernet-phy@0 { 558 compatible = "ethernet-phy-ieee802.3-c22"; 559 reg = <0>; 560 }; 561 562 ethphy1: ethernet-phy@1 { 563 compatible = "ethernet-phy-ieee802.3-c22"; 564 reg = <1>; 565 }; 566 }; 567}; 568 569&fec2 { 570 pinctrl-names = "default"; 571 pinctrl-0 = <&pinctrl_fec2>; 572 phy-mode = "rgmii-txid"; 573 phy-handle = <ðphy1>; 574 phy-supply = <®_fec2_supply>; 575 nvmem-cells = <&fec_mac1>; 576 nvmem-cell-names = "mac-address"; 577 rx-internal-delay-ps = <2000>; 578 fsl,magic-packet; 579 status = "okay"; 580}; 581 582&pciea { 583 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 584 phy-names = "pcie-phy"; 585 pinctrl-0 = <&pinctrl_pciea>; 586 pinctrl-names = "default"; 587 reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; 588 vpcie-supply = <®_pciea>; 589 status = "okay"; 590}; 591 592&pcieb { 593 phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; 594 phy-names = "pcie-phy"; 595 pinctrl-0 = <&pinctrl_pcieb>; 596 pinctrl-names = "default"; 597 reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; 598 status = "disabled"; 599}; 600 601&qm_pwm_lvds0 { 602 pinctrl-names = "default"; 603 pinctrl-0 = <&pinctrl_pwm_lvds0>; 604 status = "okay"; 605}; 606 607&pwm_lvds1 { 608 pinctrl-names = "default"; 609 pinctrl-0 = <&pinctrl_pwm_lvds1>; 610 status = "okay"; 611}; 612 613&usdhc1 { 614 pinctrl-names = "default"; 615 pinctrl-0 = <&pinctrl_usdhc1>; 616 bus-width = <8>; 617 no-sd; 618 no-sdio; 619 non-removable; 620 status = "okay"; 621}; 622 623&usdhc2 { 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_usdhc2>; 626 bus-width = <4>; 627 vmmc-supply = <®_usdhc2_vmmc>; 628 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; 629 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; 630 status = "okay"; 631}; 632 633&usb3_phy { 634 status = "okay"; 635}; 636 637&usbotg3 { 638 status = "okay"; 639}; 640 641&usbotg3_cdns3 { 642 dr_mode = "otg"; 643 usb-role-switch; 644 status = "okay"; 645 646 port { 647 usb3_drd_sw: endpoint { 648 remote-endpoint = <&typec_dr_sw>; 649 }; 650 }; 651}; 652 653&sai0 { 654 #sound-dai-cells = <0>; 655 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 656 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 657 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 658 <&sai0_lpcg IMX_LPCG_CLK_4>; 659 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&pinctrl_sai0>; 662 status = "okay"; 663}; 664 665&sai1 { 666 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 667 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 668 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 669 <&sai1_lpcg IMX_LPCG_CLK_4>; 670 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 671 pinctrl-names = "default"; 672 pinctrl-0 = <&pinctrl_sai1>; 673 status = "okay"; 674}; 675 676&sai6 { 677 assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, 678 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 679 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 680 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 681 <&sai6_lpcg IMX_LPCG_CLK_4>; 682 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 683 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 684 fsl,sai-asynchronous; 685 status = "okay"; 686}; 687 688&sai7 { 689 assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, 690 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 691 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 692 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 693 <&sai7_lpcg IMX_LPCG_CLK_4>; 694 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 695 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 696 fsl,sai-asynchronous; 697 status = "okay"; 698}; 699 700&sata { 701 status = "okay"; 702}; 703 704&vpu_dsp { 705 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 706 <&dsp_vdev0vring1>, <&dsp_reserved>; 707 status = "okay"; 708}; 709 710&iomuxc { 711 pinctrl-names = "default"; 712 pinctrl-0 = <&pinctrl_hog>; 713 714 pinctrl_hog: hoggrp { 715 fsl,pins = < 716 IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c 717 IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c 718 >; 719 }; 720 721 pinctrl_i2c0: i2c0grp { 722 fsl,pins = < 723 IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 724 IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 725 >; 726 }; 727 728 pinctrl_i2c1: i2c1grp { 729 fsl,pins = < 730 IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c 731 IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c 732 >; 733 }; 734 735 pinctrl_i2c1_gpio: i2c1gpio-grp { 736 fsl,pins = < 737 IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c 738 IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c 739 >; 740 }; 741 742 pinctrl_adc0: adc0grp { 743 fsl,pins = < 744 IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 745 >; 746 }; 747 748 pinctrl_cm41_i2c: cm41i2cgrp { 749 fsl,pins = < 750 IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c 751 IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c 752 >; 753 }; 754 755 pinctrl_fec1: fec1grp { 756 fsl,pins = < 757 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 758 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 759 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 760 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 761 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 762 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 763 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 764 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 765 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 766 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 767 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 768 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 769 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 770 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 771 >; 772 }; 773 774 pinctrl_lpspi2: lpspi2grp { 775 fsl,pins = < 776 IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040 777 IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040 778 IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040 779 >; 780 }; 781 782 pinctrl_lpspi2_cs: lpspi2csgrp { 783 fsl,pins = < 784 IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 785 >; 786 }; 787 788 pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { 789 fsl,pins = < 790 IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 791 IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 792 IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 793 >; 794 }; 795 796 pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { 797 fsl,pins = < 798 IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 799 IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 800 IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 801 >; 802 }; 803 804 pinctrl_flexspi0: flexspi0grp { 805 fsl,pins = < 806 IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 807 IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 808 IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 809 IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 810 IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 811 IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 812 IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 813 IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 814 IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 815 IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 816 IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 817 IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 818 IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 819 IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 820 IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 821 IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 822 >; 823 }; 824 825 pinctrl_fec2: fec2grp { 826 fsl,pins = < 827 IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 828 IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 829 IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 830 IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 831 IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 832 IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 833 IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 834 IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 835 IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 836 IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 837 IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 838 IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 839 IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 840 >; 841 }; 842 843 pinctrl_flexcan1: flexcan0grp { 844 fsl,pins = < 845 IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 846 IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 847 >; 848 }; 849 850 pinctrl_flexcan2: flexcan1grp { 851 fsl,pins = < 852 IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 853 IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 854 >; 855 }; 856 857 pinctrl_flexcan3: flexcan3grp { 858 fsl,pins = < 859 IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 860 IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 861 >; 862 }; 863 864 pinctrl_lpuart0: lpuart0grp { 865 fsl,pins = < 866 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 867 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 868 >; 869 }; 870 871 pinctrl_lpuart2: lpuart2grp { 872 fsl,pins = < 873 IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 874 IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 875 >; 876 }; 877 878 pinctrl_lpuart3: lpuart3grp { 879 fsl,pins = < 880 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 881 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 882 >; 883 }; 884 885 pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { 886 fsl,pins = < 887 IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c 888 IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c 889 >; 890 }; 891 892 pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { 893 fsl,pins = < 894 IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c 895 IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c 896 >; 897 }; 898 899 pinctrl_pciea: pcieagrp { 900 fsl,pins = < 901 IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 902 IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 903 IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 904 >; 905 }; 906 907 pinctrl_pciea_reg: pcieareggrp { 908 fsl,pins = < 909 IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000021 910 >; 911 }; 912 913 pinctrl_pcieb: pciebgrp { 914 fsl,pins = < 915 IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021 916 IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 917 IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 918 >; 919 }; 920 921 pinctrl_pwm_lvds0: pwmlvds0grp { 922 fsl,pins = < 923 IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 924 >; 925 }; 926 927 pinctrl_pwm_lvds1: pwmlvds1grp { 928 fsl,pins = < 929 IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 930 >; 931 }; 932 933 pinctrl_sai0: sai0grp { 934 fsl,pins = < 935 IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c 936 IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c 937 IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c 938 IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c 939 >; 940 }; 941 942 pinctrl_sai1: sai1grp { 943 fsl,pins = < 944 IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 945 IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 946 IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 947 IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 948 >; 949 }; 950 951 pinctrl_typec: typecgrp { 952 fsl,pins = < 953 IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 954 >; 955 }; 956 957 pinctrl_typec_mux: typecmuxgrp { 958 fsl,pins = < 959 IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 960 IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 961 >; 962 }; 963 964 pinctrl_usdhc1: usdhc1grp { 965 fsl,pins = < 966 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 967 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 968 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 969 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 970 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 971 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 972 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 973 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 974 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 975 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 976 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 977 >; 978 }; 979 980 pinctrl_usdhc2: usdhc2grp { 981 fsl,pins = < 982 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 983 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 984 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 985 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 986 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 987 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 988 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 989 >; 990 }; 991}; 992