1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7/dts-v1/; 8 9#include "imx8qm.dtsi" 10 11/ { 12 model = "Freescale i.MX8QM MEK"; 13 compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; 14 15 chosen { 16 stdout-path = &lpuart0; 17 }; 18 19 cpus { 20 /delete-node/ cpu-map; 21 /delete-node/ cpu@100; 22 /delete-node/ cpu@101; 23 }; 24 25 thermal-zones { 26 /delete-node/ cpu1-thermal; 27 }; 28 29 memory@80000000 { 30 device_type = "memory"; 31 reg = <0x00000000 0x80000000 0 0x40000000>; 32 }; 33 34 reg_usdhc2_vmmc: usdhc2-vmmc { 35 compatible = "regulator-fixed"; 36 regulator-name = "SD1_SPWR"; 37 regulator-min-microvolt = <3000000>; 38 regulator-max-microvolt = <3000000>; 39 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 40 enable-active-high; 41 }; 42}; 43 44&lpuart0 { 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_lpuart0>; 47 status = "okay"; 48}; 49 50&lpuart2 { 51 pinctrl-names = "default"; 52 pinctrl-0 = <&pinctrl_lpuart2>; 53 status = "okay"; 54}; 55 56&lpuart3 { 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_lpuart3>; 59 status = "okay"; 60}; 61 62&fec1 { 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_fec1>; 65 phy-mode = "rgmii-id"; 66 phy-handle = <ðphy0>; 67 fsl,magic-packet; 68 status = "okay"; 69 70 mdio { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 ethphy0: ethernet-phy@0 { 75 compatible = "ethernet-phy-ieee802.3-c22"; 76 reg = <0>; 77 }; 78 79 ethphy1: ethernet-phy@1 { 80 compatible = "ethernet-phy-ieee802.3-c22"; 81 reg = <1>; 82 }; 83 }; 84}; 85 86&usdhc1 { 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_usdhc1>; 89 bus-width = <8>; 90 no-sd; 91 no-sdio; 92 non-removable; 93 status = "okay"; 94}; 95 96&usdhc2 { 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_usdhc2>; 99 bus-width = <4>; 100 vmmc-supply = <®_usdhc2_vmmc>; 101 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; 102 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; 103 status = "okay"; 104}; 105 106&iomuxc { 107 pinctrl_fec1: fec1grp { 108 fsl,pins = < 109 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 110 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 111 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 112 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 113 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 114 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 115 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 116 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 117 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 118 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 119 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 120 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 121 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 122 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 123 >; 124 }; 125 126 pinctrl_lpuart0: lpuart0grp { 127 fsl,pins = < 128 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 129 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 130 >; 131 }; 132 133 pinctrl_lpuart2: lpuart2grp { 134 fsl,pins = < 135 IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 136 IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 137 >; 138 }; 139 140 pinctrl_lpuart3: lpuart3grp { 141 fsl,pins = < 142 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 143 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 144 >; 145 }; 146 147 pinctrl_usdhc1: usdhc1grp { 148 fsl,pins = < 149 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 150 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 151 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 152 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 153 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 154 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 155 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 156 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 157 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 158 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 159 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 160 >; 161 }; 162 163 pinctrl_usdhc2: usdhc2grp { 164 fsl,pins = < 165 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 166 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 167 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 168 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 169 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 170 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 171 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 172 >; 173 }; 174}; 175