xref: /linux/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts (revision e7d759f31ca295d589f7420719c311870bb3166f) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright 2019-2021 TQ-Systems GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mq-tqma8mq.dtsi"
9#include "mba8mx.dtsi"
10
11/ {
12	model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
13	compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
14	chassis-type = "embedded";
15
16	aliases {
17		eeprom0 = &eeprom3;
18		mmc0 = &usdhc1;
19		mmc1 = &usdhc2;
20		rtc0 = &pcf85063;
21		rtc1 = &snvs_rtc;
22	};
23
24	extcon_usbotg: extcon-usbotg0 {
25		compatible = "linux,extcon-usb-gpio";
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_usbcon0>;
28		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
29	};
30
31	pcie0_refclk: pcie0-refclk {
32		compatible = "fixed-clock";
33		#clock-cells = <0>;
34		clock-frequency = <100000000>;
35	};
36
37	pcie1_refclk: pcie1-refclk {
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		clock-frequency = <100000000>;
41	};
42
43	reg_otg_vbus: regulator-otg-vbus {
44		compatible = "regulator-fixed";
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_regotgvbus>;
47		regulator-name = "MBA8MQ_OTG_VBUS";
48		regulator-min-microvolt = <5000000>;
49		regulator-max-microvolt = <5000000>;
50		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
51		enable-active-high;
52	};
53
54	reg_usdhc2_vmmc: regulator-vmmc {
55		compatible = "regulator-fixed";
56		regulator-name = "VSD_3V3";
57		regulator-min-microvolt = <3300000>;
58		regulator-max-microvolt = <3300000>;
59		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
60		enable-active-high;
61	};
62};
63
64&btn2 {
65	gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
66};
67
68&gpio_leds {
69	led3 {
70		label = "led3";
71		gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
72	};
73};
74
75&i2c1 {
76	expander2: gpio@25 {
77		compatible = "nxp,pca9555";
78		reg = <0x25>;
79		gpio-controller;
80		#gpio-cells = <2>;
81		vcc-supply = <&reg_vcc_3v3>;
82		pinctrl-names = "default";
83		pinctrl-0 = <&pinctrl_expander>;
84		interrupt-parent = <&gpio1>;
85		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
86		interrupt-controller;
87		#interrupt-cells = <2>;
88
89		mpcie-rst-hog {
90			gpio-hog;
91			gpios = <13 0>;
92			output-high;
93			line-name = "MPCIE_RST#";
94		};
95	};
96};
97
98&irqsteer {
99	status = "okay";
100};
101
102&led2 {
103	gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
104};
105
106&pcie0 {
107	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
108	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
109		 <&pcie0_refclk>,
110		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
111		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
112	status = "okay";
113};
114
115/*
116 * miniPCIe, also usable for cards with USB. Therefore configure the reset as
117 * static gpio hog.
118 */
119&pcie1 {
120	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
121		 <&pcie1_refclk>,
122		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
123		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
124	status = "okay";
125};
126
127&sai3 {
128	assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
129	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
130	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
131	clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
132		<&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
133		<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
134		<&clk IMX8MQ_AUDIO_PLL2_OUT>;
135};
136
137&tlv320aic3x04 {
138	clock-names = "mclk";
139	clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>;
140};
141
142&uart1 {
143	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
144	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
145};
146
147&uart2 {
148	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
149	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
150};
151
152/* console */
153&uart3 {
154	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
155	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
156};
157
158&usb3_phy0 {
159	vbus-supply = <&reg_otg_vbus>;
160	status = "okay";
161};
162
163&usb_dwc3_0 {
164	/* we implement dual role but not full featured OTG */
165	extcon = <&extcon_usbotg>;
166	hnp-disable;
167	srp-disable;
168	adp-disable;
169	dr_mode = "otg";
170	status = "okay";
171};
172
173&usb3_phy1 {
174	status = "okay";
175};
176
177&usb_dwc3_1 {
178	status = "okay";
179	dr_mode = "host";
180};
181
182&wdog1 {
183	pinctrl-names = "default";
184	pinctrl-0 = <&pinctrl_wdog>;
185	fsl,ext-reset-output;
186	status = "okay";
187};
188
189&iomuxc {
190	pinctrl_ecspi1: ecspi1grp {
191		fsl,pins = <MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x0000004e>,
192			   <MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x0000004e>,
193			   <MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x0000004e>,
194			   <MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x0000004e>;
195	};
196
197	pinctrl_ecspi2: ecspi2grp {
198		fsl,pins = <MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x0000004e>,
199			   <MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x0000004e>,
200			   <MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x0000004e>,
201			   <MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x0000004e>;
202	};
203
204	pinctrl_expander: expandergrp {
205		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0xd6>;
206	};
207
208	pinctrl_fec1: fec1grp {
209		fsl,pins = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
210			   <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23>,
211			   <MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f>,
212			   <MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f>,
213			   <MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f>,
214			   <MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f>,
215			   <MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91>,
216			   <MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91>,
217			   <MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91>,
218			   <MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91>,
219			   <MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f>,
220			   <MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91>,
221			   <MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
222			   <MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f>;
223	};
224
225	pinctrl_gpiobutton: gpiobuttongrp {
226		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x41>,
227			   <MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x41>,
228			   <MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x41>;
229	};
230
231	pinctrl_gpioled: gpioledgrp {
232		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x41>,
233			   <MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x41>,
234			   <MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16	0x41>;
235	};
236
237	pinctrl_i2c2: i2c2grp {
238		fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000067>,
239			   <MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000067>;
240	};
241
242	pinctrl_i2c2_gpio: i2c2gpiogrp {
243		fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000067>,
244			   <MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000067>;
245	};
246
247	pinctrl_i2c3: i2c3grp {
248		fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000067>,
249			   <MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000067>;
250	};
251
252	pinctrl_i2c3_gpio: i2c3gpiogrp {
253		fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000067>,
254			   <MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000067>;
255	};
256
257	pinctrl_pwm3: pwm3grp {
258		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT		0x16>;
259	};
260
261	pinctrl_pwm4: pwm4grp {
262		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT		0x16>;
263	};
264
265	pinctrl_regotgvbus: reggotgvbusgrp {
266		/* USB1 OTG PWR as GPIO */
267		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x06>;
268	};
269
270	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
271		fsl,pins = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0xc1>;
272	};
273
274	pinctrl_sai3: sai3grp {
275		fsl,pins = <MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK		0xd6>,
276			   <MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0xd6>,
277			   <MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0xd6>,
278			   <MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0xd6>,
279			   <MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6>,
280			   <MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6>,
281			   <MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6>;
282	};
283
284	pinctrl_uart1: uart1grp {
285		fsl,pins = <MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79>,
286			   <MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79>;
287	};
288
289	pinctrl_uart2: uart2grp {
290		fsl,pins = <MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x79>,
291			   <MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x79>;
292	};
293
294	pinctrl_uart3: uart3grp {
295		fsl,pins = <MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x79>,
296			   <MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x79>;
297	};
298
299	pinctrl_uart4: uart4grp {
300		fsl,pins = <MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX		0x79>,
301			   <MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX		0x79>;
302	};
303
304	pinctrl_usbcon0: usb0congrp {
305		/* ID: floating / high: device, low: host -> use PU */
306		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0xe6>;
307	};
308
309	pinctrl_usdhc2: usdhc2grp {
310		fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83>,
311			   <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3>,
312			   <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3>,
313			   <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3>,
314			   <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3>,
315			   <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3>,
316			   <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1>;
317	};
318
319	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
320		fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85>,
321			   <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5>,
322			   <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5>,
323			   <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5>,
324			   <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5>,
325			   <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5>,
326			   <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1>;
327	};
328
329	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
330		fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f>,
331			   <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7>,
332			   <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7>,
333			   <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7>,
334			   <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7>,
335			   <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7>,
336			   <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1>;
337	};
338
339	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
340		fsl,pins = <MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41>;
341	};
342};
343