1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019 Einfochips 4 * Copyright 2019 Linaro Ltd. 5 */ 6 7/dts-v1/; 8 9#include "imx8mq.dtsi" 10 11/ { 12 model = "Einfochips i.MX8MQ Thor96"; 13 compatible = "einfochips,imx8mq-thor96", "fsl,imx8mq"; 14 15 chosen { 16 stdout-path = &uart1; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x00000000 0x40000000 0 0x80000000>; 22 }; 23 24 leds { 25 compatible = "gpio-leds"; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_leds>; 28 29 user-led1 { 30 label = "green:user1"; 31 gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; 32 linux,default-trigger = "heartbeat"; 33 }; 34 35 user-led2 { 36 label = "green:user2"; 37 gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; 38 linux,default-trigger = "none"; 39 }; 40 41 user-led3 { 42 label = "green:user3"; 43 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 44 linux,default-trigger = "mmc1"; 45 default-state = "off"; 46 }; 47 48 user-led4 { 49 label = "green:user4"; 50 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 51 panic-indicator; 52 linux,default-trigger = "none"; 53 }; 54 55 wlan-active-led { 56 label = "yellow:wlan"; 57 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 58 linux,default-trigger = "phy0tx"; 59 default-state = "off"; 60 }; 61 62 bt-active-led { 63 label = "blue:bt"; 64 gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; 65 linux,default-trigger = "hci0-power"; 66 default-state = "off"; 67 }; 68 }; 69 70 reg_usdhc1_vmmc: reg-usdhc1-vmmc { 71 compatible = "regulator-fixed"; 72 regulator-name = "VDD_3V3"; 73 regulator-min-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>; 75 regulator-always-on; 76 }; 77 78 reg_usdhc1_vqmmc: reg-usdhc1-vqmmc { 79 compatible = "regulator-fixed"; 80 regulator-name = "VCC_1V8_EXT"; 81 regulator-min-microvolt = <1800000>; 82 regulator-max-microvolt = <1800000>; 83 regulator-always-on; 84 }; 85 86 reg_usdhc2_vmmc: reg-usdhc2-vmmc { 87 compatible = "regulator-fixed"; 88 regulator-name = "VSD_3V3"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 regulator-always-on; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_reg_usdhc2>; 94 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 95 enable-active-high; 96 }; 97 98 reg_usdhc2_vqmmc: reg-usdhc2-vqmmc { 99 compatible = "regulator-fixed"; 100 regulator-name = "NVCC_SD2"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 regulator-always-on; 104 }; 105 106 sdio_pwrseq: sdio-pwrseq { 107 compatible = "mmc-pwrseq-simple"; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_wifi_reg_on>; 110 reset-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 111 }; 112}; 113 114/* LS-SPI0 */ 115&ecspi2 { 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_ecspi2>; 118 status = "okay"; 119}; 120 121&fec1 { 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_fec1>; 124 phy-mode = "rgmii-id"; 125 phy-handle = <ðphy>; 126 fsl,magic-packet; 127 status = "okay"; 128 129 mdio { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 ethphy: ethernet-phy@3 { 134 compatible = "ethernet-phy-ieee802.3-c22"; 135 reg = <3>; 136 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 137 }; 138 }; 139}; 140 141/* LS-I2C0 */ 142&i2c1 { 143 clock-frequency = <100000>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_i2c1>; 146 status = "okay"; 147 148 pmic@8 { 149 compatible = "fsl,pfuze100"; 150 reg = <0x8>; 151 152 regulators { 153 sw1a_reg: sw1ab { 154 regulator-min-microvolt = <300000>; 155 regulator-max-microvolt = <1875000>; 156 }; 157 158 sw1c_reg: sw1c { 159 regulator-min-microvolt = <300000>; 160 regulator-max-microvolt = <1875000>; 161 }; 162 163 sw2_reg: sw2 { 164 regulator-min-microvolt = <800000>; 165 regulator-max-microvolt = <3300000>; 166 regulator-always-on; 167 }; 168 169 sw3a_reg: sw3ab { 170 regulator-min-microvolt = <400000>; 171 regulator-max-microvolt = <1975000>; 172 regulator-always-on; 173 }; 174 175 sw4_reg: sw4 { 176 regulator-min-microvolt = <800000>; 177 regulator-max-microvolt = <3300000>; 178 regulator-always-on; 179 }; 180 181 swbst_reg: swbst { 182 regulator-min-microvolt = <5000000>; 183 regulator-max-microvolt = <5150000>; 184 }; 185 186 snvs_reg: vsnvs { 187 regulator-min-microvolt = <1000000>; 188 regulator-max-microvolt = <3000000>; 189 regulator-always-on; 190 }; 191 192 vref_reg: vrefddr { 193 regulator-always-on; 194 }; 195 196 vgen1_reg: vgen1 { 197 regulator-min-microvolt = <800000>; 198 regulator-max-microvolt = <1550000>; 199 }; 200 201 vgen2_reg: vgen2 { 202 regulator-min-microvolt = <800000>; 203 regulator-max-microvolt = <1550000>; 204 regulator-always-on; 205 }; 206 207 vgen3_reg: vgen3 { 208 regulator-min-microvolt = <1800000>; 209 regulator-max-microvolt = <3300000>; 210 regulator-always-on; 211 }; 212 213 vgen4_reg: vgen4 { 214 regulator-min-microvolt = <1800000>; 215 regulator-max-microvolt = <3300000>; 216 regulator-always-on; 217 }; 218 219 vgen5_reg: vgen5 { 220 regulator-min-microvolt = <1800000>; 221 regulator-max-microvolt = <3300000>; 222 regulator-always-on; 223 }; 224 225 vgen6_reg: vgen6 { 226 regulator-min-microvolt = <1800000>; 227 regulator-max-microvolt = <3300000>; 228 }; 229 }; 230 }; 231}; 232 233/* LS-I2C1 */ 234&i2c2 { 235 clock-frequency = <100000>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_i2c2>; 238 status = "okay"; 239 240 eeprom: eeprom@50 { 241 compatible = "atmel,24c256"; 242 reg = <0x50>; 243 }; 244}; 245 246/* HS-I2C2 */ 247&i2c3 { 248 clock-frequency = <100000>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_i2c3>; 251 status = "okay"; 252}; 253 254/* HS-I2C3 */ 255&i2c4 { 256 clock-frequency = <100000>; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_i2c4>; 259 status = "okay"; 260}; 261 262&pgc_gpu { 263 power-supply = <&sw1a_reg>; 264}; 265 266&pgc_vpu { 267 power-supply = <&sw1c_reg>; 268}; 269 270&qspi0 { 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_qspi0>; 273 status = "okay"; 274 275 flash@0 { 276 compatible = "jedec,spi-nor"; 277 spi-max-frequency = <100000000>; 278 reg = <0>; 279 }; 280}; 281 282/* Debug UART */ 283&uart1 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_uart1>; 286 assigned-clocks = <&clk IMX8MQ_CLK_UART1>; 287 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 288 status = "okay"; 289}; 290 291/* LS-UART0 */ 292&uart2 { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_uart2>; 295 assigned-clocks = <&clk IMX8MQ_CLK_UART2>; 296 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 297 uart-has-rtscts; 298 status = "okay"; 299 300 bluetooth { 301 compatible = "brcm,bcm43438-bt"; 302 device-wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; 303 host-wakeup-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; 304 shutdown-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_bt_gpios>; 307 }; 308}; 309 310/* LS-UART1 */ 311&uart3 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_uart3>; 314 assigned-clocks = <&clk IMX8MQ_CLK_UART3>; 315 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 316 status = "okay"; 317}; 318 319&usb3_phy1 { 320 status = "okay"; 321}; 322 323&usb_dwc3_1 { 324 dr_mode = "host"; 325 status = "okay"; 326}; 327 328/* SDIO */ 329&usdhc1 { 330 #address-cells = <0x1>; 331 #size-cells = <0x0>; 332 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 333 pinctrl-0 = <&pinctrl_usdhc1>; 334 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 335 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 336 vmmc-supply = <®_usdhc1_vmmc>; 337 vqmmc-supply = <®_usdhc1_vqmmc>; 338 mmc-pwrseq = <&sdio_pwrseq>; 339 bus-width = <4>; 340 non-removable; 341 no-sd; 342 no-mmc; 343 status = "okay"; 344 345 brcmf: wifi@1 { 346 reg = <1>; 347 compatible = "brcm,bcm4329-fmac"; 348 }; 349}; 350 351/* uSD */ 352&usdhc2 { 353 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 354 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 355 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 356 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 357 vmmc-supply = <®_usdhc2_vmmc>; 358 vqmmc-supply = <®_usdhc2_vqmmc>; 359 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 360 bus-width = <4>; 361 no-sdio; 362 no-mmc; 363 disable-wp; 364 status = "okay"; 365}; 366 367&wdog1 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_wdog>; 370 fsl,ext-reset-output; 371 status = "okay"; 372}; 373 374&iomuxc { 375 pinctrl_bt_gpios: btgpiosgrp { 376 fsl,pins = < 377 MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 378 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 379 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 380 >; 381 }; 382 383 pinctrl_ecspi2: ecspi2grp { 384 fsl,pins = < 385 MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x16 386 MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x16 387 MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x16 388 MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x16 389 >; 390 }; 391 392 pinctrl_fec1: fec1grp { 393 fsl,pins = < 394 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x4 395 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x24 396 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1c 397 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1c 398 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1c 399 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1c 400 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 401 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 402 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 403 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 404 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1c 405 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 406 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 407 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1c 408 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 409 >; 410 }; 411 412 pinctrl_i2c1: i2c1grp { 413 fsl,pins = < 414 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 415 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 416 >; 417 }; 418 419 pinctrl_i2c2: i2c2grp { 420 fsl,pins = < 421 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 422 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 423 >; 424 }; 425 426 pinctrl_i2c3: i2c3grp { 427 fsl,pins = < 428 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f 429 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f 430 >; 431 }; 432 433 pinctrl_i2c4: i2c4grp { 434 fsl,pins = < 435 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f 436 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f 437 >; 438 }; 439 440 pinctrl_leds: ledsgrp { 441 fsl,pins = < 442 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x19 443 MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 444 MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 445 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 446 MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 447 MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 448 >; 449 }; 450 451 pinctrl_qspi0: qspi0grp { 452 fsl,pins = < 453 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 454 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 455 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 456 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 457 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 458 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 459 460 >; 461 }; 462 463 pinctrl_reg_usdhc2: regusdhc2grp { 464 fsl,pins = < 465 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 466 >; 467 }; 468 469 pinctrl_uart1: uart1grp { 470 fsl,pins = < 471 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 472 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 473 >; 474 }; 475 476 pinctrl_uart2: uart2grp { 477 fsl,pins = < 478 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 479 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 480 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 481 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 482 >; 483 }; 484 485 pinctrl_uart3: uart3grp { 486 fsl,pins = < 487 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 488 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 489 >; 490 }; 491 492 pinctrl_usdhc1: usdhc1grp { 493 fsl,pins = < 494 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 495 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 496 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 497 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 498 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 499 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 500 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 501 >; 502 }; 503 504 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 505 fsl,pins = < 506 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 507 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 508 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 509 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 510 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 511 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 512 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 513 >; 514 }; 515 516 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 517 fsl,pins = < 518 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 519 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 520 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 521 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 522 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 523 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 524 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 525 >; 526 }; 527 528 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 529 fsl,pins = < 530 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 531 >; 532 }; 533 534 pinctrl_usdhc2: usdhc2grp { 535 fsl,pins = < 536 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 537 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 538 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 539 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 540 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 541 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 542 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 543 >; 544 }; 545 546 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 547 fsl,pins = < 548 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8c 549 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcc 550 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcc 551 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcc 552 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcc 553 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcc 554 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 555 >; 556 }; 557 558 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 559 fsl,pins = < 560 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9c 561 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdc 562 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdc 563 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdc 564 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdc 565 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdc 566 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xcc 567 >; 568 }; 569 570 pinctrl_wdog: wdoggrp { 571 fsl,pins = < 572 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 573 >; 574 }; 575 576 pinctrl_wifi_reg_on: wifiregongrp { 577 fsl,pins = < 578 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 579 >; 580 }; 581}; 582