xref: /linux/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts (revision 58d416351e6df1a41d415958ccdd8eb9c2173fed) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3/*
4 * Copyright 2019-2021 MNT Research GmbH
5 * Copyright 2021 Lucas Stach <dev@lynxeye.de>
6 */
7
8/dts-v1/;
9
10#include "imx8mq-nitrogen-som.dtsi"
11
12/ {
13	model = "MNT Reform 2";
14	compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
15	chassis-type = "laptop";
16
17	backlight: backlight {
18		compatible = "pwm-backlight";
19		pinctrl-names = "default";
20		pinctrl-0 = <&pinctrl_backlight>;
21		pwms = <&pwm2 0 10000>;
22		power-supply = <&reg_main_usb>;
23		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
24		brightness-levels = <0 32 64 128 160 200 255>;
25		default-brightness-level = <6>;
26	};
27
28	panel {
29		compatible = "innolux,n125hce-gn1", "simple-panel";
30		power-supply = <&reg_main_3v3>;
31		backlight = <&backlight>;
32		no-hpd;
33
34		port {
35			panel_in: endpoint {
36				remote-endpoint = <&edp_bridge_out>;
37			};
38		};
39	};
40
41	pcie1_refclk: clock-pcie1-refclk {
42		compatible = "fixed-clock";
43		#clock-cells = <0>;
44		clock-frequency = <100000000>;
45	};
46
47	reg_main_5v: regulator-main-5v {
48		compatible = "regulator-fixed";
49		regulator-name = "5V";
50		regulator-min-microvolt = <5000000>;
51		regulator-max-microvolt = <5000000>;
52	};
53
54	reg_main_3v3: regulator-main-3v3 {
55		compatible = "regulator-fixed";
56		regulator-name = "3V3";
57		regulator-min-microvolt = <3300000>;
58		regulator-max-microvolt = <3300000>;
59	};
60
61	reg_main_usb: regulator-main-usb {
62		compatible = "regulator-fixed";
63		regulator-name = "USB_PWR";
64		regulator-min-microvolt = <5000000>;
65		regulator-max-microvolt = <5000000>;
66		vin-supply = <&reg_main_5v>;
67	};
68
69	reg_main_1v8: regulator-main-1v8 {
70		compatible = "regulator-fixed";
71		regulator-name = "1V8";
72		regulator-min-microvolt = <1800000>;
73		regulator-max-microvolt = <1800000>;
74		vin-supply = <&reg_main_3v3>;
75	};
76
77	reg_main_1v2: regulator-main-1v2 {
78		compatible = "regulator-fixed";
79		regulator-name = "1V2";
80		regulator-min-microvolt = <1200000>;
81		regulator-max-microvolt = <1200000>;
82		vin-supply = <&reg_main_5v>;
83	};
84
85	sound {
86		compatible = "fsl,imx-audio-wm8960";
87		audio-cpu = <&sai2>;
88		audio-codec = <&wm8960>;
89		audio-routing =
90			"Headphone Jack", "HP_L",
91			"Headphone Jack", "HP_R",
92			"Ext Spk", "SPK_LP",
93			"Ext Spk", "SPK_LN",
94			"Ext Spk", "SPK_RP",
95			"Ext Spk", "SPK_RN",
96			"LINPUT1", "Mic Jack",
97			"Mic Jack", "MICB",
98			"LINPUT2", "Line In Jack",
99			"RINPUT2", "Line In Jack";
100		model = "wm8960-audio";
101	};
102};
103
104&dphy {
105	assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
106	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
107	assigned-clock-rates = <25000000>;
108	status = "okay";
109};
110
111&fec1 {
112	status = "okay";
113};
114
115&i2c3 {
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_i2c3>;
118	status = "okay";
119
120	wm8960: codec@1a {
121		compatible = "wlf,wm8960";
122		reg = <0x1a>;
123		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
124		clock-names = "mclk";
125		#sound-dai-cells = <0>;
126	};
127
128	rtc@68 {
129		compatible = "nxp,pcf8523";
130		reg = <0x68>;
131	};
132};
133
134&i2c4 {
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_i2c4>;
137	clock-frequency = <400000>;
138	status = "okay";
139
140	edp_bridge: bridge@2c {
141		compatible = "ti,sn65dsi86";
142		pinctrl-names = "default";
143		pinctrl-0 = <&pinctrl_edp_bridge>;
144		reg = <0x2c>;
145		enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
146		vccio-supply = <&reg_main_1v8>;
147		vpll-supply = <&reg_main_1v8>;
148		vcca-supply = <&reg_main_1v2>;
149		vcc-supply = <&reg_main_1v2>;
150
151		ports {
152			#address-cells = <1>;
153			#size-cells = <0>;
154
155			port@0 {
156				reg = <0>;
157
158				edp_bridge_in: endpoint {
159					remote-endpoint = <&mipi_dsi_out>;
160				};
161			};
162
163			port@1 {
164				reg = <1>;
165
166				edp_bridge_out: endpoint {
167					remote-endpoint = <&panel_in>;
168				};
169			};
170		};
171	};
172};
173
174&lcdif {
175	assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
176	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
177	/delete-property/assigned-clock-rates;
178	status = "okay";
179};
180
181&mipi_dsi {
182	status = "okay";
183
184	ports {
185		port@1 {
186			reg = <1>;
187
188			mipi_dsi_out: endpoint {
189				remote-endpoint = <&edp_bridge_in>;
190			};
191		};
192	};
193};
194
195&pcie1 {
196	pinctrl-names = "default";
197	pinctrl-0 = <&pinctrl_pcie1>;
198	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
199	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
200		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
201		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
202		 <&pcie1_refclk>;
203	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
204	status = "okay";
205};
206
207&pwm2 {
208	pinctrl-names = "default";
209	pinctrl-0 = <&pinctrl_pwm2>;
210	status = "okay";
211};
212
213
214&reg_1p8v {
215	vin-supply = <&reg_main_5v>;
216};
217
218&reg_snvs {
219	vin-supply = <&reg_main_5v>;
220};
221
222&reg_arm_dram {
223	vin-supply = <&reg_main_5v>;
224};
225
226&reg_dram_1p1v {
227	vin-supply = <&reg_main_5v>;
228};
229
230&reg_soc_gpu_vpu {
231	vin-supply = <&reg_main_5v>;
232};
233
234&sai2 {
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_sai2>;
237	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
238	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
239	assigned-clock-rates = <25000000>;
240	fsl,sai-mclk-direction-output;
241	fsl,sai-asynchronous;
242	status = "okay";
243};
244
245&snvs_rtc {
246	status = "disabled";
247};
248
249&uart2 {
250	pinctrl-names = "default";
251	pinctrl-0 = <&pinctrl_uart2>;
252	status = "okay";
253};
254
255&usb3_phy0 {
256	vbus-supply = <&reg_main_usb>;
257	status = "okay";
258};
259
260&usb3_phy1 {
261	vbus-supply = <&reg_main_usb>;
262	status = "okay";
263};
264
265&usb_dwc3_0 {
266	dr_mode = "host";
267	status = "okay";
268};
269
270&usb_dwc3_1 {
271	dr_mode = "host";
272	status = "okay";
273};
274
275&usdhc2 {
276	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
277	assigned-clock-rates = <200000000>;
278	pinctrl-names = "default";
279	pinctrl-0 = <&pinctrl_usdhc2>;
280	vqmmc-supply = <&reg_main_3v3>;
281	vmmc-supply = <&reg_main_3v3>;
282	bus-width = <4>;
283	status = "okay";
284};
285
286&iomuxc {
287	pinctrl_backlight: backlightgrp {
288		fsl,pins = <
289			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x3
290		>;
291	};
292
293	pinctrl_edp_bridge: edpbridgegrp {
294		fsl,pins = <
295			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x1
296		>;
297	};
298
299	pinctrl_i2c3: i2c3grp {
300		fsl,pins = <
301			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000022
302			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000022
303		>;
304	};
305
306	pinctrl_i2c4: i2c4grp {
307		fsl,pins = <
308			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000022
309			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000022
310		>;
311	};
312
313	pinctrl_pcie1: pcie1grp {
314		fsl,pins = <
315			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
316		>;
317	};
318
319	pinctrl_pwm2: pwm2grp {
320		fsl,pins = <
321			MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT			0x3
322		>;
323	};
324
325	pinctrl_sai2: sai2grp {
326		fsl,pins = <
327			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6
328			MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6
329			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6
330			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6
331			MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK		0xd6
332			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6
333			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6
334		>;
335	};
336
337	pinctrl_uart2: uart2grp {
338		fsl,pins = <
339			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45
340			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45
341		>;
342	};
343
344	pinctrl_usdhc2: usdhc2grp {
345		fsl,pins = <
346			MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0
347			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
348			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
349			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
350			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
351			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
352			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
353		>;
354	};
355};
356