1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7/dts-v1/; 8 9#include "imx8mq.dtsi" 10 11/ { 12 model = "NXP i.MX8MQ EVK"; 13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; 14 15 chosen { 16 stdout-path = &uart1; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x00000000 0x40000000 0 0xc0000000>; 22 }; 23 24 pcie0_refclk: pcie0-refclk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <100000000>; 28 }; 29 30 reg_pcie1: regulator-pcie { 31 compatible = "regulator-fixed"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_pcie1_reg>; 34 regulator-name = "MPCIE_3V3"; 35 regulator-min-microvolt = <3300000>; 36 regulator-max-microvolt = <3300000>; 37 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; 38 enable-active-high; 39 }; 40 41 reg_usdhc2_vmmc: regulator-vsd-3v3 { 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_reg_usdhc2>; 44 compatible = "regulator-fixed"; 45 regulator-name = "VSD_3V3"; 46 regulator-min-microvolt = <3300000>; 47 regulator-max-microvolt = <3300000>; 48 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 49 off-on-delay-us = <20000>; 50 enable-active-high; 51 }; 52 53 buck2_reg: regulator-buck2 { 54 pinctrl-names = "default"; 55 pinctrl-0 = <&pinctrl_buck2>; 56 compatible = "regulator-gpio"; 57 regulator-name = "vdd_arm"; 58 regulator-min-microvolt = <900000>; 59 regulator-max-microvolt = <1000000>; 60 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 61 states = <1000000 0x0 62 900000 0x1>; 63 regulator-boot-on; 64 regulator-always-on; 65 }; 66 67 ir-receiver { 68 compatible = "gpio-ir-receiver"; 69 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 70 pinctrl-names = "default"; 71 pinctrl-0 = <&pinctrl_ir>; 72 linux,autosuspend-period = <125>; 73 }; 74 75 audio_codec_bt_sco: audio-codec-bt-sco { 76 compatible = "linux,bt-sco"; 77 #sound-dai-cells = <1>; 78 }; 79 80 wm8524: audio-codec { 81 #sound-dai-cells = <0>; 82 compatible = "wlf,wm8524"; 83 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 84 }; 85 86 sound-bt-sco { 87 compatible = "simple-audio-card"; 88 simple-audio-card,name = "bt-sco-audio"; 89 simple-audio-card,format = "dsp_a"; 90 simple-audio-card,bitclock-inversion; 91 simple-audio-card,frame-master = <&btcpu>; 92 simple-audio-card,bitclock-master = <&btcpu>; 93 94 btcpu: simple-audio-card,cpu { 95 sound-dai = <&sai3>; 96 dai-tdm-slot-num = <2>; 97 dai-tdm-slot-width = <16>; 98 }; 99 100 simple-audio-card,codec { 101 sound-dai = <&audio_codec_bt_sco 1>; 102 }; 103 }; 104 105 sound-wm8524 { 106 compatible = "simple-audio-card"; 107 simple-audio-card,name = "wm8524-audio"; 108 simple-audio-card,format = "i2s"; 109 simple-audio-card,frame-master = <&cpudai>; 110 simple-audio-card,bitclock-master = <&cpudai>; 111 simple-audio-card,mclk-fs = <256>; 112 simple-audio-card,widgets = 113 "Line", "Left Line Out Jack", 114 "Line", "Right Line Out Jack"; 115 simple-audio-card,routing = 116 "Left Line Out Jack", "LINEVOUTL", 117 "Right Line Out Jack", "LINEVOUTR"; 118 119 cpudai: simple-audio-card,cpu { 120 sound-dai = <&sai2>; 121 system-clock-direction-out; 122 }; 123 124 link_codec: simple-audio-card,codec { 125 sound-dai = <&wm8524>; 126 }; 127 }; 128 129 spdif_out: spdif-out { 130 compatible = "linux,spdif-dit"; 131 #sound-dai-cells = <0>; 132 }; 133 134 spdif_in: spdif-in { 135 compatible = "linux,spdif-dir"; 136 #sound-dai-cells = <0>; 137 }; 138 139 sound-spdif { 140 compatible = "fsl,imx-audio-spdif"; 141 model = "imx-spdif"; 142 audio-cpu = <&spdif1>; 143 audio-codec = <&spdif_out>, <&spdif_in>; 144 }; 145 146 hdmi_arc_in: hdmi-arc-in { 147 compatible = "linux,spdif-dir"; 148 #sound-dai-cells = <0>; 149 }; 150 151 sound-hdmi-arc { 152 compatible = "fsl,imx-audio-spdif"; 153 model = "imx-hdmi-arc"; 154 audio-cpu = <&spdif2>; 155 audio-codec = <&hdmi_arc_in>; 156 }; 157}; 158 159&A53_0 { 160 cpu-supply = <&buck2_reg>; 161}; 162 163&A53_1 { 164 cpu-supply = <&buck2_reg>; 165}; 166 167&A53_2 { 168 cpu-supply = <&buck2_reg>; 169}; 170 171&A53_3 { 172 cpu-supply = <&buck2_reg>; 173}; 174 175&ddrc { 176 operating-points-v2 = <&ddrc_opp_table>; 177 status = "okay"; 178 179 ddrc_opp_table: opp-table { 180 compatible = "operating-points-v2"; 181 182 opp-25000000 { 183 opp-hz = /bits/ 64 <25000000>; 184 }; 185 186 opp-100000000 { 187 opp-hz = /bits/ 64 <100000000>; 188 }; 189 190 /* 191 * On imx8mq B0 PLL can't be bypassed so low bus is 166M 192 */ 193 opp-166000000 { 194 opp-hz = /bits/ 64 <166935483>; 195 }; 196 197 opp-800000000 { 198 opp-hz = /bits/ 64 <800000000>; 199 }; 200 }; 201}; 202 203&dphy { 204 status = "okay"; 205}; 206 207&fec1 { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_fec1>; 210 phy-mode = "rgmii-id"; 211 phy-handle = <ðphy0>; 212 fsl,magic-packet; 213 status = "okay"; 214 215 mdio { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 219 ethphy0: ethernet-phy@0 { 220 compatible = "ethernet-phy-ieee802.3-c22"; 221 reg = <0>; 222 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 223 reset-assert-us = <10000>; 224 qca,disable-smarteee; 225 vddio-supply = <&vddh>; 226 227 vddh: vddh-regulator { 228 }; 229 }; 230 }; 231}; 232 233&gpio5 { 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_wifi_reset>; 236 237 wl-reg-on-hog { 238 gpio-hog; 239 gpios = <29 GPIO_ACTIVE_HIGH>; 240 output-high; 241 }; 242}; 243 244&i2c1 { 245 clock-frequency = <100000>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_i2c1>; 248 status = "okay"; 249 250 pmic@8 { 251 compatible = "fsl,pfuze100"; 252 reg = <0x8>; 253 254 regulators { 255 sw1a_reg: sw1ab { 256 regulator-min-microvolt = <825000>; 257 regulator-max-microvolt = <1100000>; 258 }; 259 260 sw1c_reg: sw1c { 261 regulator-min-microvolt = <825000>; 262 regulator-max-microvolt = <1100000>; 263 }; 264 265 sw2_reg: sw2 { 266 regulator-min-microvolt = <1100000>; 267 regulator-max-microvolt = <1100000>; 268 regulator-always-on; 269 }; 270 271 sw3a_reg: sw3ab { 272 regulator-min-microvolt = <825000>; 273 regulator-max-microvolt = <1100000>; 274 regulator-always-on; 275 }; 276 277 sw4_reg: sw4 { 278 regulator-min-microvolt = <1800000>; 279 regulator-max-microvolt = <1800000>; 280 regulator-always-on; 281 }; 282 283 swbst_reg: swbst { 284 regulator-min-microvolt = <5000000>; 285 regulator-max-microvolt = <5150000>; 286 }; 287 288 snvs_reg: vsnvs { 289 regulator-min-microvolt = <1000000>; 290 regulator-max-microvolt = <3000000>; 291 regulator-always-on; 292 }; 293 294 vref_reg: vrefddr { 295 regulator-always-on; 296 }; 297 298 vgen1_reg: vgen1 { 299 regulator-min-microvolt = <800000>; 300 regulator-max-microvolt = <1550000>; 301 }; 302 303 vgen2_reg: vgen2 { 304 regulator-min-microvolt = <850000>; 305 regulator-max-microvolt = <975000>; 306 regulator-always-on; 307 }; 308 309 vgen3_reg: vgen3 { 310 regulator-min-microvolt = <1675000>; 311 regulator-max-microvolt = <1975000>; 312 regulator-always-on; 313 }; 314 315 vgen4_reg: vgen4 { 316 regulator-min-microvolt = <1625000>; 317 regulator-max-microvolt = <1875000>; 318 regulator-always-on; 319 }; 320 321 vgen5_reg: vgen5 { 322 regulator-min-microvolt = <3075000>; 323 regulator-max-microvolt = <3625000>; 324 regulator-always-on; 325 }; 326 327 vgen6_reg: vgen6 { 328 regulator-min-microvolt = <1800000>; 329 regulator-max-microvolt = <3300000>; 330 }; 331 }; 332 }; 333}; 334 335&lcdif { 336 status = "okay"; 337}; 338 339&mipi_dsi { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 status = "okay"; 343 344 panel@0 { 345 pinctrl-0 = <&pinctrl_mipi_dsi>; 346 pinctrl-names = "default"; 347 compatible = "raydium,rm67191"; 348 reg = <0>; 349 reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; 350 dsi-lanes = <4>; 351 352 port { 353 panel_in: endpoint { 354 remote-endpoint = <&mipi_dsi_out>; 355 }; 356 }; 357 }; 358 359 ports { 360 port@1 { 361 reg = <1>; 362 mipi_dsi_out: endpoint { 363 remote-endpoint = <&panel_in>; 364 }; 365 }; 366 }; 367}; 368 369&pcie0 { 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_pcie0>; 372 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; 373 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 374 <&pcie0_refclk>, 375 <&clk IMX8MQ_CLK_PCIE1_PHY>, 376 <&clk IMX8MQ_CLK_PCIE1_AUX>; 377 vph-supply = <&vgen5_reg>; 378 status = "okay"; 379}; 380 381&pcie0_ep { 382 pinctrl-names = "default"; 383 pinctrl-0 = <&pinctrl_pcie0>; 384 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 385 <&pcie0_refclk>, 386 <&clk IMX8MQ_CLK_PCIE1_PHY>, 387 <&clk IMX8MQ_CLK_PCIE1_AUX>; 388 status = "disabled"; 389}; 390 391&pcie1 { 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_pcie1>; 394 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; 395 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 396 <&pcie0_refclk>, 397 <&clk IMX8MQ_CLK_PCIE2_PHY>, 398 <&clk IMX8MQ_CLK_PCIE2_AUX>; 399 vpcie-supply = <®_pcie1>; 400 vph-supply = <&vgen5_reg>; 401 status = "okay"; 402}; 403 404&pcie1_ep { 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pinctrl_pcie1>; 407 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 408 <&pcie0_refclk>, 409 <&clk IMX8MQ_CLK_PCIE2_PHY>, 410 <&clk IMX8MQ_CLK_PCIE2_AUX>; 411 status = "disabled"; 412}; 413 414&pgc_gpu { 415 power-supply = <&sw1a_reg>; 416}; 417 418&pgc_vpu { 419 power-supply = <&sw1c_reg>; 420}; 421 422&qspi0 { 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pinctrl_qspi>; 425 status = "okay"; 426 427 n25q256a: flash@0 { 428 reg = <0>; 429 #address-cells = <1>; 430 #size-cells = <1>; 431 compatible = "micron,n25q256a", "jedec,spi-nor"; 432 spi-max-frequency = <29000000>; 433 spi-tx-bus-width = <1>; 434 spi-rx-bus-width = <4>; 435 }; 436}; 437 438&sai2 { 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pinctrl_sai2>; 441 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; 442 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; 443 assigned-clock-rates = <0>, <24576000>; 444 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, <&clk IMX8MQ_CLK_DUMMY>, 445 <&clk IMX8MQ_CLK_SAI2_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, 446 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, 447 <&clk IMX8MQ_AUDIO_PLL2_OUT>; 448 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 449 status = "okay"; 450}; 451 452&sai3 { 453 #sound-dai-cells = <0>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&pinctrl_sai3>; 456 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; 457 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 458 assigned-clock-rates = <24576000>; 459 status = "okay"; 460}; 461 462&snvs_pwrkey { 463 status = "okay"; 464}; 465 466&spdif1 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_spdif1>; 469 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; 470 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 471 assigned-clock-rates = <24576000>; 472 status = "okay"; 473}; 474 475&spdif2 { 476 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; 477 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 478 assigned-clock-rates = <24576000>; 479 status = "okay"; 480}; 481 482&uart1 { 483 pinctrl-names = "default"; 484 pinctrl-0 = <&pinctrl_uart1>; 485 status = "okay"; 486}; 487 488&usb3_phy1 { 489 status = "okay"; 490}; 491 492&usb_dwc3_1 { 493 dr_mode = "host"; 494 status = "okay"; 495}; 496 497&usdhc1 { 498 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 499 assigned-clock-rates = <400000000>; 500 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 501 pinctrl-0 = <&pinctrl_usdhc1>; 502 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 503 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 504 vqmmc-supply = <&sw4_reg>; 505 bus-width = <8>; 506 non-removable; 507 no-sd; 508 no-sdio; 509 status = "okay"; 510}; 511 512&usdhc2 { 513 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 514 assigned-clock-rates = <200000000>; 515 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 516 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 517 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 518 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 519 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 520 vmmc-supply = <®_usdhc2_vmmc>; 521 status = "okay"; 522}; 523 524&wdog1 { 525 pinctrl-names = "default"; 526 pinctrl-0 = <&pinctrl_wdog>; 527 fsl,ext-reset-output; 528 status = "okay"; 529}; 530 531&iomuxc { 532 pinctrl_buck2: vddarmgrp { 533 fsl,pins = < 534 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 535 >; 536 }; 537 538 pinctrl_fec1: fec1grp { 539 fsl,pins = < 540 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 541 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 542 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 543 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 544 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 545 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 546 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 547 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 548 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 549 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 550 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 551 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 552 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 553 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 554 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 555 >; 556 }; 557 558 pinctrl_i2c1: i2c1grp { 559 fsl,pins = < 560 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 561 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 562 >; 563 }; 564 565 pinctrl_ir: irgrp { 566 fsl,pins = < 567 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f 568 >; 569 }; 570 571 pinctrl_mipi_dsi: mipidsigrp { 572 fsl,pins = < 573 MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 574 >; 575 }; 576 577 pinctrl_pcie0: pcie0grp { 578 fsl,pins = < 579 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 580 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 581 >; 582 }; 583 584 pinctrl_pcie1: pcie1grp { 585 fsl,pins = < 586 MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 587 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 588 >; 589 }; 590 591 pinctrl_pcie1_reg: pcie1reggrp { 592 fsl,pins = < 593 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 594 >; 595 }; 596 597 pinctrl_qspi: qspigrp { 598 fsl,pins = < 599 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 600 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 601 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 602 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 603 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 604 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 605 >; 606 }; 607 608 pinctrl_reg_usdhc2: regusdhc2gpiogrp { 609 fsl,pins = < 610 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 611 >; 612 }; 613 614 pinctrl_sai2: sai2grp { 615 fsl,pins = < 616 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 617 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 618 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 619 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 620 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 621 >; 622 }; 623 624 pinctrl_sai3: sai3grp { 625 fsl,pins = < 626 MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 627 MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 628 MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 629 MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 630 >; 631 }; 632 633 pinctrl_spdif1: spdif1grp { 634 fsl,pins = < 635 MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 636 MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 637 >; 638 }; 639 640 pinctrl_uart1: uart1grp { 641 fsl,pins = < 642 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 643 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 644 >; 645 }; 646 647 pinctrl_usdhc1: usdhc1grp { 648 fsl,pins = < 649 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 650 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 651 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 652 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 653 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 654 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 655 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 656 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 657 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 658 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 659 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 660 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 661 >; 662 }; 663 664 pinctrl_usdhc1_100mhz: usdhc1-100grp { 665 fsl,pins = < 666 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 667 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 668 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 669 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 670 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 671 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 672 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 673 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 674 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 675 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 676 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 677 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 678 >; 679 }; 680 681 pinctrl_usdhc1_200mhz: usdhc1-200grp { 682 fsl,pins = < 683 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 684 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 685 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 686 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 687 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 688 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 689 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 690 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 691 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 692 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 693 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 694 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 695 >; 696 }; 697 698 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 699 fsl,pins = < 700 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 701 >; 702 }; 703 704 pinctrl_usdhc2: usdhc2grp { 705 fsl,pins = < 706 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 707 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 708 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 709 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 710 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 711 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 712 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 713 >; 714 }; 715 716 pinctrl_usdhc2_100mhz: usdhc2-100grp { 717 fsl,pins = < 718 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 719 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 720 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 721 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 722 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 723 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 724 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 725 >; 726 }; 727 728 pinctrl_usdhc2_200mhz: usdhc2-200grp { 729 fsl,pins = < 730 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 731 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 732 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 733 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 734 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 735 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 736 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 737 >; 738 }; 739 740 pinctrl_wdog: wdog1grp { 741 fsl,pins = < 742 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 743 >; 744 }; 745 746 pinctrl_wifi_reset: wifiresetgrp { 747 fsl,pins = < 748 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 749 >; 750 }; 751}; 752