1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7/dts-v1/; 8 9#include "imx8mq.dtsi" 10 11/ { 12 model = "NXP i.MX8MQ EVK"; 13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; 14 15 chosen { 16 stdout-path = &uart1; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x00000000 0x40000000 0 0xc0000000>; 22 }; 23 24 pcie0_refclk: pcie0-refclk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <100000000>; 28 }; 29 30 reg_usdhc2_vmmc: regulator-vsd-3v3 { 31 pinctrl-names = "default"; 32 pinctrl-0 = <&pinctrl_reg_usdhc2>; 33 compatible = "regulator-fixed"; 34 regulator-name = "VSD_3V3"; 35 regulator-min-microvolt = <3300000>; 36 regulator-max-microvolt = <3300000>; 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 38 enable-active-high; 39 }; 40 41 buck2_reg: regulator-buck2 { 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_buck2>; 44 compatible = "regulator-gpio"; 45 regulator-name = "vdd_arm"; 46 regulator-min-microvolt = <900000>; 47 regulator-max-microvolt = <1000000>; 48 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 49 states = <1000000 0x0 50 900000 0x1>; 51 regulator-boot-on; 52 regulator-always-on; 53 }; 54 55 ir-receiver { 56 compatible = "gpio-ir-receiver"; 57 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_ir>; 60 }; 61 62 wm8524: audio-codec { 63 #sound-dai-cells = <0>; 64 compatible = "wlf,wm8524"; 65 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 66 }; 67 68 sound-wm8524 { 69 compatible = "simple-audio-card"; 70 simple-audio-card,name = "wm8524-audio"; 71 simple-audio-card,format = "i2s"; 72 simple-audio-card,frame-master = <&cpudai>; 73 simple-audio-card,bitclock-master = <&cpudai>; 74 simple-audio-card,widgets = 75 "Line", "Left Line Out Jack", 76 "Line", "Right Line Out Jack"; 77 simple-audio-card,routing = 78 "Left Line Out Jack", "LINEVOUTL", 79 "Right Line Out Jack", "LINEVOUTR"; 80 81 cpudai: simple-audio-card,cpu { 82 sound-dai = <&sai2>; 83 }; 84 85 link_codec: simple-audio-card,codec { 86 sound-dai = <&wm8524>; 87 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 88 }; 89 }; 90}; 91 92&A53_0 { 93 cpu-supply = <&buck2_reg>; 94}; 95 96&A53_1 { 97 cpu-supply = <&buck2_reg>; 98}; 99 100&A53_2 { 101 cpu-supply = <&buck2_reg>; 102}; 103 104&A53_3 { 105 cpu-supply = <&buck2_reg>; 106}; 107 108&fec1 { 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_fec1>; 111 phy-mode = "rgmii-id"; 112 phy-handle = <ðphy0>; 113 fsl,magic-packet; 114 status = "okay"; 115 116 mdio { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 ethphy0: ethernet-phy@0 { 121 compatible = "ethernet-phy-ieee802.3-c22"; 122 reg = <0>; 123 }; 124 }; 125}; 126 127&gpio5 { 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_wifi_reset>; 130 131 wl-reg-on { 132 gpio-hog; 133 gpios = <29 GPIO_ACTIVE_HIGH>; 134 output-high; 135 }; 136}; 137 138&i2c1 { 139 clock-frequency = <100000>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_i2c1>; 142 status = "okay"; 143 144 pmic@8 { 145 compatible = "fsl,pfuze100"; 146 reg = <0x8>; 147 148 regulators { 149 sw1a_reg: sw1ab { 150 regulator-min-microvolt = <825000>; 151 regulator-max-microvolt = <1100000>; 152 }; 153 154 sw1c_reg: sw1c { 155 regulator-min-microvolt = <825000>; 156 regulator-max-microvolt = <1100000>; 157 }; 158 159 sw2_reg: sw2 { 160 regulator-min-microvolt = <1100000>; 161 regulator-max-microvolt = <1100000>; 162 regulator-always-on; 163 }; 164 165 sw3a_reg: sw3ab { 166 regulator-min-microvolt = <825000>; 167 regulator-max-microvolt = <1100000>; 168 regulator-always-on; 169 }; 170 171 sw4_reg: sw4 { 172 regulator-min-microvolt = <1800000>; 173 regulator-max-microvolt = <1800000>; 174 regulator-always-on; 175 }; 176 177 swbst_reg: swbst { 178 regulator-min-microvolt = <5000000>; 179 regulator-max-microvolt = <5150000>; 180 }; 181 182 snvs_reg: vsnvs { 183 regulator-min-microvolt = <1000000>; 184 regulator-max-microvolt = <3000000>; 185 regulator-always-on; 186 }; 187 188 vref_reg: vrefddr { 189 regulator-always-on; 190 }; 191 192 vgen1_reg: vgen1 { 193 regulator-min-microvolt = <800000>; 194 regulator-max-microvolt = <1550000>; 195 }; 196 197 vgen2_reg: vgen2 { 198 regulator-min-microvolt = <850000>; 199 regulator-max-microvolt = <975000>; 200 regulator-always-on; 201 }; 202 203 vgen3_reg: vgen3 { 204 regulator-min-microvolt = <1675000>; 205 regulator-max-microvolt = <1975000>; 206 regulator-always-on; 207 }; 208 209 vgen4_reg: vgen4 { 210 regulator-min-microvolt = <1625000>; 211 regulator-max-microvolt = <1875000>; 212 regulator-always-on; 213 }; 214 215 vgen5_reg: vgen5 { 216 regulator-min-microvolt = <3075000>; 217 regulator-max-microvolt = <3625000>; 218 regulator-always-on; 219 }; 220 221 vgen6_reg: vgen6 { 222 regulator-min-microvolt = <1800000>; 223 regulator-max-microvolt = <3300000>; 224 }; 225 }; 226 }; 227}; 228 229&pcie0 { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_pcie0>; 232 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; 233 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 234 <&clk IMX8MQ_CLK_PCIE1_AUX>, 235 <&clk IMX8MQ_CLK_PCIE1_PHY>, 236 <&pcie0_refclk>; 237 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; 238 status = "okay"; 239}; 240 241&pgc_gpu { 242 power-supply = <&sw1a_reg>; 243}; 244 245&qspi0 { 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_qspi>; 248 status = "okay"; 249 250 n25q256a: flash@0 { 251 reg = <0>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 compatible = "micron,n25q256a", "jedec,spi-nor"; 255 spi-max-frequency = <29000000>; 256 }; 257}; 258 259&sai2 { 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_sai2>; 262 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; 263 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; 264 assigned-clock-rates = <0>, <24576000>; 265 status = "okay"; 266}; 267 268&snvs_pwrkey { 269 status = "okay"; 270}; 271 272&uart1 { 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_uart1>; 275 status = "okay"; 276}; 277 278&usb3_phy1 { 279 status = "okay"; 280}; 281 282&usb_dwc3_1 { 283 dr_mode = "host"; 284 status = "okay"; 285}; 286 287&usdhc1 { 288 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 289 assigned-clock-rates = <400000000>; 290 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 291 pinctrl-0 = <&pinctrl_usdhc1>; 292 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 293 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 294 vqmmc-supply = <&sw4_reg>; 295 bus-width = <8>; 296 non-removable; 297 no-sd; 298 no-sdio; 299 status = "okay"; 300}; 301 302&usdhc2 { 303 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 304 assigned-clock-rates = <200000000>; 305 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 306 pinctrl-0 = <&pinctrl_usdhc2>; 307 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 308 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 309 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 310 vmmc-supply = <®_usdhc2_vmmc>; 311 status = "okay"; 312}; 313 314&wdog1 { 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_wdog>; 317 fsl,ext-reset-output; 318 status = "okay"; 319}; 320 321&iomuxc { 322 pinctrl_buck2: vddarmgrp { 323 fsl,pins = < 324 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 325 >; 326 327 }; 328 329 pinctrl_fec1: fec1grp { 330 fsl,pins = < 331 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 332 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 333 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 334 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 335 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 336 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 337 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 338 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 339 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 340 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 341 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 342 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 343 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 344 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 345 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 346 >; 347 }; 348 349 pinctrl_i2c1: i2c1grp { 350 fsl,pins = < 351 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 352 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 353 >; 354 }; 355 356 pinctrl_ir: irgrp { 357 fsl,pins = < 358 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f 359 >; 360 }; 361 362 pinctrl_pcie0: pcie0grp { 363 fsl,pins = < 364 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 365 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 366 >; 367 }; 368 369 pinctrl_qspi: qspigrp { 370 fsl,pins = < 371 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 372 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 373 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 374 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 375 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 376 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 377 378 >; 379 }; 380 381 pinctrl_reg_usdhc2: regusdhc2grpgpio { 382 fsl,pins = < 383 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 384 >; 385 }; 386 387 pinctrl_sai2: sai2grp { 388 fsl,pins = < 389 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 390 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 391 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 392 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 393 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 394 >; 395 }; 396 397 pinctrl_uart1: uart1grp { 398 fsl,pins = < 399 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 400 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 401 >; 402 }; 403 404 pinctrl_usdhc1: usdhc1grp { 405 fsl,pins = < 406 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 407 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 408 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 409 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 410 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 411 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 412 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 413 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 414 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 415 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 416 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 417 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 418 >; 419 }; 420 421 pinctrl_usdhc1_100mhz: usdhc1-100grp { 422 fsl,pins = < 423 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 424 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 425 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 426 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 427 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 428 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 429 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 430 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 431 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 432 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 433 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 434 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 435 >; 436 }; 437 438 pinctrl_usdhc1_200mhz: usdhc1-200grp { 439 fsl,pins = < 440 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 441 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 442 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 443 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 444 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 445 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 446 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 447 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 448 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 449 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 450 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 451 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 452 >; 453 }; 454 455 pinctrl_usdhc2: usdhc2grp { 456 fsl,pins = < 457 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 458 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 459 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 460 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 461 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 462 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 463 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 464 >; 465 }; 466 467 pinctrl_usdhc2_100mhz: usdhc2-100grp { 468 fsl,pins = < 469 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 470 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 471 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 472 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 473 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 474 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 475 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 476 >; 477 }; 478 479 pinctrl_usdhc2_200mhz: usdhc2-200grp { 480 fsl,pins = < 481 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 482 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 483 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 484 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 485 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 486 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 487 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 488 >; 489 }; 490 491 pinctrl_wdog: wdog1grp { 492 fsl,pins = < 493 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 494 >; 495 }; 496 497 pinctrl_wifi_reset: wifiresetgrp { 498 fsl,pins = < 499 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 500 >; 501 }; 502}; 503