1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 funnel { 206 /* 207 * non-configurable funnel don't show up on the AMBA 208 * bus. As such no need to add "arm,primecell". 209 */ 210 compatible = "arm,coresight-static-funnel"; 211 212 in-ports { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 216 port@0 { 217 reg = <0>; 218 219 ca_funnel_in_port0: endpoint { 220 remote-endpoint = <&etm0_out_port>; 221 }; 222 }; 223 224 port@1 { 225 reg = <1>; 226 227 ca_funnel_in_port1: endpoint { 228 remote-endpoint = <&etm1_out_port>; 229 }; 230 }; 231 232 port@2 { 233 reg = <2>; 234 235 ca_funnel_in_port2: endpoint { 236 remote-endpoint = <&etm2_out_port>; 237 }; 238 }; 239 240 port@3 { 241 reg = <3>; 242 243 ca_funnel_in_port3: endpoint { 244 remote-endpoint = <&etm3_out_port>; 245 }; 246 }; 247 }; 248 249 out-ports { 250 port { 251 252 ca_funnel_out_port0: endpoint { 253 remote-endpoint = <&hugo_funnel_in_port0>; 254 }; 255 }; 256 }; 257 }; 258 259 reserved-memory { 260 #address-cells = <2>; 261 #size-cells = <2>; 262 ranges; 263 264 dsp_reserved: dsp@92400000 { 265 reg = <0 0x92400000 0 0x2000000>; 266 no-map; 267 status = "disabled"; 268 }; 269 }; 270 271 pmu { 272 compatible = "arm,cortex-a53-pmu"; 273 interrupts = <GIC_PPI 7 274 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 275 }; 276 277 psci { 278 compatible = "arm,psci-1.0"; 279 method = "smc"; 280 }; 281 282 thermal-zones { 283 cpu-thermal { 284 polling-delay-passive = <250>; 285 polling-delay = <2000>; 286 thermal-sensors = <&tmu 0>; 287 trips { 288 cpu_alert0: trip0 { 289 temperature = <85000>; 290 hysteresis = <2000>; 291 type = "passive"; 292 }; 293 294 cpu_crit0: trip1 { 295 temperature = <95000>; 296 hysteresis = <2000>; 297 type = "critical"; 298 }; 299 }; 300 301 cooling-maps { 302 map0 { 303 trip = <&cpu_alert0>; 304 cooling-device = 305 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 306 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 307 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 308 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 309 }; 310 }; 311 }; 312 313 soc-thermal { 314 polling-delay-passive = <250>; 315 polling-delay = <2000>; 316 thermal-sensors = <&tmu 1>; 317 trips { 318 soc_alert0: trip0 { 319 temperature = <85000>; 320 hysteresis = <2000>; 321 type = "passive"; 322 }; 323 324 soc_crit0: trip1 { 325 temperature = <95000>; 326 hysteresis = <2000>; 327 type = "critical"; 328 }; 329 }; 330 331 cooling-maps { 332 map0 { 333 trip = <&soc_alert0>; 334 cooling-device = 335 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 336 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 337 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 338 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 339 }; 340 }; 341 }; 342 }; 343 344 timer { 345 compatible = "arm,armv8-timer"; 346 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 347 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 348 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 349 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 350 clock-frequency = <8000000>; 351 arm,no-tick-in-suspend; 352 }; 353 354 soc: soc@0 { 355 compatible = "fsl,imx8mp-soc", "simple-bus"; 356 #address-cells = <1>; 357 #size-cells = <1>; 358 ranges = <0x0 0x0 0x0 0x3e000000>; 359 nvmem-cells = <&imx8mp_uid>; 360 nvmem-cell-names = "soc_unique_id"; 361 362 etm0: etm@28440000 { 363 compatible = "arm,coresight-etm4x", "arm,primecell"; 364 reg = <0x28440000 0x1000>; 365 cpu = <&A53_0>; 366 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 367 clock-names = "apb_pclk"; 368 369 out-ports { 370 port { 371 etm0_out_port: endpoint { 372 remote-endpoint = <&ca_funnel_in_port0>; 373 }; 374 }; 375 }; 376 }; 377 378 etm1: etm@28540000 { 379 compatible = "arm,coresight-etm4x", "arm,primecell"; 380 reg = <0x28540000 0x1000>; 381 cpu = <&A53_1>; 382 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 383 clock-names = "apb_pclk"; 384 385 out-ports { 386 port { 387 etm1_out_port: endpoint { 388 remote-endpoint = <&ca_funnel_in_port1>; 389 }; 390 }; 391 }; 392 }; 393 394 etm2: etm@28640000 { 395 compatible = "arm,coresight-etm4x", "arm,primecell"; 396 reg = <0x28640000 0x1000>; 397 cpu = <&A53_2>; 398 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 399 clock-names = "apb_pclk"; 400 401 out-ports { 402 port { 403 etm2_out_port: endpoint { 404 remote-endpoint = <&ca_funnel_in_port2>; 405 }; 406 }; 407 }; 408 }; 409 410 etm3: etm@28740000 { 411 compatible = "arm,coresight-etm4x", "arm,primecell"; 412 reg = <0x28740000 0x1000>; 413 cpu = <&A53_3>; 414 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 415 clock-names = "apb_pclk"; 416 417 out-ports { 418 port { 419 etm3_out_port: endpoint { 420 remote-endpoint = <&ca_funnel_in_port3>; 421 }; 422 }; 423 }; 424 }; 425 426 funnel@28c03000 { 427 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 428 reg = <0x28c03000 0x1000>; 429 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 430 clock-names = "apb_pclk"; 431 432 in-ports { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 436 port@0 { 437 reg = <0>; 438 439 hugo_funnel_in_port0: endpoint { 440 remote-endpoint = <&ca_funnel_out_port0>; 441 }; 442 }; 443 444 port@1 { 445 reg = <1>; 446 447 hugo_funnel_in_port1: endpoint { 448 /* M7 input */ 449 }; 450 }; 451 452 port@2 { 453 reg = <2>; 454 455 hugo_funnel_in_port2: endpoint { 456 /* DSP input */ 457 }; 458 }; 459 /* the other input ports are not connect to anything */ 460 }; 461 462 out-ports { 463 port { 464 hugo_funnel_out_port0: endpoint { 465 remote-endpoint = <&etf_in_port>; 466 }; 467 }; 468 }; 469 }; 470 471 etf@28c04000 { 472 compatible = "arm,coresight-tmc", "arm,primecell"; 473 reg = <0x28c04000 0x1000>; 474 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 475 clock-names = "apb_pclk"; 476 477 in-ports { 478 port { 479 etf_in_port: endpoint { 480 remote-endpoint = <&hugo_funnel_out_port0>; 481 }; 482 }; 483 }; 484 485 out-ports { 486 port { 487 etf_out_port: endpoint { 488 remote-endpoint = <&etr_in_port>; 489 }; 490 }; 491 }; 492 }; 493 494 etr@28c06000 { 495 compatible = "arm,coresight-tmc", "arm,primecell"; 496 reg = <0x28c06000 0x1000>; 497 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 498 clock-names = "apb_pclk"; 499 500 in-ports { 501 port { 502 etr_in_port: endpoint { 503 remote-endpoint = <&etf_out_port>; 504 }; 505 }; 506 }; 507 }; 508 509 aips1: bus@30000000 { 510 compatible = "fsl,aips-bus", "simple-bus"; 511 reg = <0x30000000 0x400000>; 512 #address-cells = <1>; 513 #size-cells = <1>; 514 ranges; 515 516 gpio1: gpio@30200000 { 517 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 518 reg = <0x30200000 0x10000>; 519 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 522 gpio-controller; 523 #gpio-cells = <2>; 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 gpio-ranges = <&iomuxc 0 5 30>; 527 }; 528 529 gpio2: gpio@30210000 { 530 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 531 reg = <0x30210000 0x10000>; 532 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 535 gpio-controller; 536 #gpio-cells = <2>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 gpio-ranges = <&iomuxc 0 35 21>; 540 }; 541 542 gpio3: gpio@30220000 { 543 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 544 reg = <0x30220000 0x10000>; 545 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 548 gpio-controller; 549 #gpio-cells = <2>; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 553 }; 554 555 gpio4: gpio@30230000 { 556 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 557 reg = <0x30230000 0x10000>; 558 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 561 gpio-controller; 562 #gpio-cells = <2>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 gpio-ranges = <&iomuxc 0 82 32>; 566 }; 567 568 gpio5: gpio@30240000 { 569 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 570 reg = <0x30240000 0x10000>; 571 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 gpio-ranges = <&iomuxc 0 114 30>; 579 }; 580 581 tmu: tmu@30260000 { 582 compatible = "fsl,imx8mp-tmu"; 583 reg = <0x30260000 0x10000>; 584 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 585 nvmem-cells = <&tmu_calib>; 586 nvmem-cell-names = "calib"; 587 #thermal-sensor-cells = <1>; 588 }; 589 590 wdog1: watchdog@30280000 { 591 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 592 reg = <0x30280000 0x10000>; 593 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 595 status = "disabled"; 596 }; 597 598 wdog2: watchdog@30290000 { 599 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 600 reg = <0x30290000 0x10000>; 601 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 603 status = "disabled"; 604 }; 605 606 wdog3: watchdog@302a0000 { 607 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 608 reg = <0x302a0000 0x10000>; 609 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 611 status = "disabled"; 612 }; 613 614 gpt1: timer@302d0000 { 615 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 616 reg = <0x302d0000 0x10000>; 617 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 619 clock-names = "ipg", "per"; 620 }; 621 622 gpt2: timer@302e0000 { 623 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 624 reg = <0x302e0000 0x10000>; 625 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 627 clock-names = "ipg", "per"; 628 }; 629 630 gpt3: timer@302f0000 { 631 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 632 reg = <0x302f0000 0x10000>; 633 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 635 clock-names = "ipg", "per"; 636 }; 637 638 iomuxc: pinctrl@30330000 { 639 compatible = "fsl,imx8mp-iomuxc"; 640 reg = <0x30330000 0x10000>; 641 }; 642 643 gpr: syscon@30340000 { 644 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 645 reg = <0x30340000 0x10000>; 646 }; 647 648 ocotp: efuse@30350000 { 649 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 650 reg = <0x30350000 0x10000>; 651 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 652 /* For nvmem subnodes */ 653 #address-cells = <1>; 654 #size-cells = <1>; 655 656 /* 657 * The register address below maps to the MX8M 658 * Fusemap Description Table entries this way. 659 * Assuming 660 * reg = <ADDR SIZE>; 661 * then 662 * Fuse Address = (ADDR * 4) + 0x400 663 * Note that if SIZE is greater than 4, then 664 * each subsequent fuse is located at offset 665 * +0x10 in Fusemap Description Table (e.g. 666 * reg = <0x8 0x8> describes fuses 0x420 and 667 * 0x430). 668 */ 669 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 670 reg = <0x8 0x8>; 671 }; 672 673 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 674 reg = <0x10 4>; 675 }; 676 677 eth_mac1: mac-address@90 { /* 0x640 */ 678 reg = <0x90 6>; 679 }; 680 681 eth_mac2: mac-address@96 { /* 0x658 */ 682 reg = <0x96 6>; 683 }; 684 685 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 686 reg = <0x264 0x10>; 687 }; 688 }; 689 690 anatop: clock-controller@30360000 { 691 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 692 reg = <0x30360000 0x10000>; 693 #clock-cells = <1>; 694 }; 695 696 snvs: snvs@30370000 { 697 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 698 reg = <0x30370000 0x10000>; 699 700 snvs_rtc: snvs-rtc-lp { 701 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 702 regmap = <&snvs>; 703 offset = <0x34>; 704 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 707 clock-names = "snvs-rtc"; 708 }; 709 710 snvs_pwrkey: snvs-powerkey { 711 compatible = "fsl,sec-v4.0-pwrkey"; 712 regmap = <&snvs>; 713 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 715 clock-names = "snvs-pwrkey"; 716 linux,keycode = <KEY_POWER>; 717 wakeup-source; 718 status = "disabled"; 719 }; 720 721 snvs_lpgpr: snvs-lpgpr { 722 compatible = "fsl,imx8mp-snvs-lpgpr", 723 "fsl,imx7d-snvs-lpgpr"; 724 }; 725 }; 726 727 clk: clock-controller@30380000 { 728 compatible = "fsl,imx8mp-ccm"; 729 reg = <0x30380000 0x10000>; 730 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 732 #clock-cells = <1>; 733 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 734 <&clk_ext3>, <&clk_ext4>; 735 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 736 "clk_ext3", "clk_ext4"; 737 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 738 <&clk IMX8MP_CLK_A53_CORE>, 739 <&clk IMX8MP_CLK_NOC>, 740 <&clk IMX8MP_CLK_NOC_IO>, 741 <&clk IMX8MP_CLK_GIC>; 742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 743 <&clk IMX8MP_ARM_PLL_OUT>, 744 <&clk IMX8MP_SYS_PLL2_1000M>, 745 <&clk IMX8MP_SYS_PLL1_800M>, 746 <&clk IMX8MP_SYS_PLL2_500M>; 747 assigned-clock-rates = <0>, <0>, 748 <1000000000>, 749 <800000000>, 750 <500000000>; 751 }; 752 753 src: reset-controller@30390000 { 754 compatible = "fsl,imx8mp-src", "syscon"; 755 reg = <0x30390000 0x10000>; 756 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 757 #reset-cells = <1>; 758 }; 759 760 gpc: gpc@303a0000 { 761 compatible = "fsl,imx8mp-gpc"; 762 reg = <0x303a0000 0x1000>; 763 interrupt-parent = <&gic>; 764 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-controller; 766 #interrupt-cells = <3>; 767 768 pgc { 769 #address-cells = <1>; 770 #size-cells = <0>; 771 772 pgc_mipi_phy1: power-domain@0 { 773 #power-domain-cells = <0>; 774 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 775 }; 776 777 pgc_pcie_phy: power-domain@1 { 778 #power-domain-cells = <0>; 779 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 780 }; 781 782 pgc_usb1_phy: power-domain@2 { 783 #power-domain-cells = <0>; 784 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 785 }; 786 787 pgc_usb2_phy: power-domain@3 { 788 #power-domain-cells = <0>; 789 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 790 }; 791 792 pgc_mlmix: power-domain@4 { 793 #power-domain-cells = <0>; 794 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 795 clocks = <&clk IMX8MP_CLK_ML_AXI>, 796 <&clk IMX8MP_CLK_ML_AHB>, 797 <&clk IMX8MP_CLK_NPU_ROOT>; 798 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 799 <&clk IMX8MP_CLK_ML_AXI>, 800 <&clk IMX8MP_CLK_ML_AHB>; 801 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 802 <&clk IMX8MP_SYS_PLL1_800M>, 803 <&clk IMX8MP_SYS_PLL1_800M>; 804 assigned-clock-rates = <800000000>, 805 <800000000>, 806 <300000000>; 807 }; 808 809 pgc_audio: power-domain@5 { 810 #power-domain-cells = <0>; 811 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; 812 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 813 <&clk IMX8MP_CLK_AUDIO_AXI>; 814 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, 815 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; 816 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 817 <&clk IMX8MP_SYS_PLL1_800M>; 818 assigned-clock-rates = <400000000>, 819 <600000000>; 820 }; 821 822 pgc_gpu2d: power-domain@6 { 823 #power-domain-cells = <0>; 824 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 825 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 826 power-domains = <&pgc_gpumix>; 827 }; 828 829 pgc_gpumix: power-domain@7 { 830 #power-domain-cells = <0>; 831 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 832 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 833 <&clk IMX8MP_CLK_GPU_AHB>; 834 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 835 <&clk IMX8MP_CLK_GPU_AHB>; 836 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 837 <&clk IMX8MP_SYS_PLL1_800M>; 838 assigned-clock-rates = <800000000>, <400000000>; 839 }; 840 841 pgc_vpumix: power-domain@8 { 842 #power-domain-cells = <0>; 843 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 844 clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 845 }; 846 847 pgc_gpu3d: power-domain@9 { 848 #power-domain-cells = <0>; 849 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 850 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 851 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 852 power-domains = <&pgc_gpumix>; 853 }; 854 855 pgc_mediamix: power-domain@10 { 856 #power-domain-cells = <0>; 857 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 858 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 859 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 860 }; 861 862 pgc_vpu_g1: power-domain@11 { 863 #power-domain-cells = <0>; 864 power-domains = <&pgc_vpumix>; 865 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 866 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 867 }; 868 869 pgc_vpu_g2: power-domain@12 { 870 #power-domain-cells = <0>; 871 power-domains = <&pgc_vpumix>; 872 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 873 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 874 875 }; 876 877 pgc_vpu_vc8000e: power-domain@13 { 878 #power-domain-cells = <0>; 879 power-domains = <&pgc_vpumix>; 880 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 881 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 882 }; 883 884 pgc_hdmimix: power-domain@14 { 885 #power-domain-cells = <0>; 886 reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; 887 clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, 888 <&clk IMX8MP_CLK_HDMI_APB>; 889 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, 890 <&clk IMX8MP_CLK_HDMI_APB>; 891 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, 892 <&clk IMX8MP_SYS_PLL1_133M>; 893 assigned-clock-rates = <500000000>, <133000000>; 894 }; 895 896 pgc_hdmi_phy: power-domain@15 { 897 #power-domain-cells = <0>; 898 reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; 899 }; 900 901 pgc_mipi_phy2: power-domain@16 { 902 #power-domain-cells = <0>; 903 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 904 }; 905 906 pgc_hsiomix: power-domain@17 { 907 #power-domain-cells = <0>; 908 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 909 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 910 <&clk IMX8MP_CLK_HSIO_ROOT>; 911 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 912 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 913 assigned-clock-rates = <500000000>; 914 }; 915 916 pgc_ispdwp: power-domain@18 { 917 #power-domain-cells = <0>; 918 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 919 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 920 }; 921 }; 922 }; 923 }; 924 925 aips2: bus@30400000 { 926 compatible = "fsl,aips-bus", "simple-bus"; 927 reg = <0x30400000 0x400000>; 928 #address-cells = <1>; 929 #size-cells = <1>; 930 ranges; 931 932 pwm1: pwm@30660000 { 933 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 934 reg = <0x30660000 0x10000>; 935 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 937 <&clk IMX8MP_CLK_PWM1_ROOT>; 938 clock-names = "ipg", "per"; 939 #pwm-cells = <3>; 940 status = "disabled"; 941 }; 942 943 pwm2: pwm@30670000 { 944 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 945 reg = <0x30670000 0x10000>; 946 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 948 <&clk IMX8MP_CLK_PWM2_ROOT>; 949 clock-names = "ipg", "per"; 950 #pwm-cells = <3>; 951 status = "disabled"; 952 }; 953 954 pwm3: pwm@30680000 { 955 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 956 reg = <0x30680000 0x10000>; 957 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 959 <&clk IMX8MP_CLK_PWM3_ROOT>; 960 clock-names = "ipg", "per"; 961 #pwm-cells = <3>; 962 status = "disabled"; 963 }; 964 965 pwm4: pwm@30690000 { 966 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 967 reg = <0x30690000 0x10000>; 968 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 970 <&clk IMX8MP_CLK_PWM4_ROOT>; 971 clock-names = "ipg", "per"; 972 #pwm-cells = <3>; 973 status = "disabled"; 974 }; 975 976 system_counter: timer@306a0000 { 977 compatible = "nxp,sysctr-timer"; 978 reg = <0x306a0000 0x20000>; 979 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&osc_24m>; 981 clock-names = "per"; 982 }; 983 984 gpt6: timer@306e0000 { 985 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 986 reg = <0x306e0000 0x10000>; 987 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 989 clock-names = "ipg", "per"; 990 }; 991 992 gpt5: timer@306f0000 { 993 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 994 reg = <0x306f0000 0x10000>; 995 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 997 clock-names = "ipg", "per"; 998 }; 999 1000 gpt4: timer@30700000 { 1001 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1002 reg = <0x30700000 0x10000>; 1003 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 1005 clock-names = "ipg", "per"; 1006 }; 1007 }; 1008 1009 aips3: bus@30800000 { 1010 compatible = "fsl,aips-bus", "simple-bus"; 1011 reg = <0x30800000 0x400000>; 1012 #address-cells = <1>; 1013 #size-cells = <1>; 1014 ranges; 1015 1016 spba-bus@30800000 { 1017 compatible = "fsl,spba-bus", "simple-bus"; 1018 reg = <0x30800000 0x100000>; 1019 #address-cells = <1>; 1020 #size-cells = <1>; 1021 ranges; 1022 1023 ecspi1: spi@30820000 { 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1027 reg = <0x30820000 0x10000>; 1028 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 1030 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 1031 clock-names = "ipg", "per"; 1032 assigned-clock-rates = <80000000>; 1033 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 1034 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1035 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 1036 dma-names = "rx", "tx"; 1037 status = "disabled"; 1038 }; 1039 1040 ecspi2: spi@30830000 { 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1044 reg = <0x30830000 0x10000>; 1045 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 1047 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 1048 clock-names = "ipg", "per"; 1049 assigned-clock-rates = <80000000>; 1050 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 1051 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1052 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1053 dma-names = "rx", "tx"; 1054 status = "disabled"; 1055 }; 1056 1057 ecspi3: spi@30840000 { 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1061 reg = <0x30840000 0x10000>; 1062 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 1064 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 1065 clock-names = "ipg", "per"; 1066 assigned-clock-rates = <80000000>; 1067 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 1068 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1069 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1070 dma-names = "rx", "tx"; 1071 status = "disabled"; 1072 }; 1073 1074 uart1: serial@30860000 { 1075 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1076 reg = <0x30860000 0x10000>; 1077 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 1079 <&clk IMX8MP_CLK_UART1_ROOT>; 1080 clock-names = "ipg", "per"; 1081 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1082 dma-names = "rx", "tx"; 1083 status = "disabled"; 1084 }; 1085 1086 uart3: serial@30880000 { 1087 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1088 reg = <0x30880000 0x10000>; 1089 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 1091 <&clk IMX8MP_CLK_UART3_ROOT>; 1092 clock-names = "ipg", "per"; 1093 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1094 dma-names = "rx", "tx"; 1095 status = "disabled"; 1096 }; 1097 1098 uart2: serial@30890000 { 1099 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1100 reg = <0x30890000 0x10000>; 1101 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 1103 <&clk IMX8MP_CLK_UART2_ROOT>; 1104 clock-names = "ipg", "per"; 1105 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1106 dma-names = "rx", "tx"; 1107 status = "disabled"; 1108 }; 1109 1110 flexcan1: can@308c0000 { 1111 compatible = "fsl,imx8mp-flexcan"; 1112 reg = <0x308c0000 0x10000>; 1113 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1115 <&clk IMX8MP_CLK_CAN1_ROOT>; 1116 clock-names = "ipg", "per"; 1117 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 1118 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1119 assigned-clock-rates = <40000000>; 1120 fsl,clk-source = /bits/ 8 <0>; 1121 fsl,stop-mode = <&gpr 0x10 4>; 1122 status = "disabled"; 1123 }; 1124 1125 flexcan2: can@308d0000 { 1126 compatible = "fsl,imx8mp-flexcan"; 1127 reg = <0x308d0000 0x10000>; 1128 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1130 <&clk IMX8MP_CLK_CAN2_ROOT>; 1131 clock-names = "ipg", "per"; 1132 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 1133 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1134 assigned-clock-rates = <40000000>; 1135 fsl,clk-source = /bits/ 8 <0>; 1136 fsl,stop-mode = <&gpr 0x10 5>; 1137 status = "disabled"; 1138 }; 1139 }; 1140 1141 crypto: crypto@30900000 { 1142 compatible = "fsl,sec-v4.0"; 1143 #address-cells = <1>; 1144 #size-cells = <1>; 1145 reg = <0x30900000 0x40000>; 1146 ranges = <0 0x30900000 0x40000>; 1147 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&clk IMX8MP_CLK_AHB>, 1149 <&clk IMX8MP_CLK_IPG_ROOT>; 1150 clock-names = "aclk", "ipg"; 1151 1152 sec_jr0: jr@1000 { 1153 compatible = "fsl,sec-v4.0-job-ring"; 1154 reg = <0x1000 0x1000>; 1155 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1156 status = "disabled"; 1157 }; 1158 1159 sec_jr1: jr@2000 { 1160 compatible = "fsl,sec-v4.0-job-ring"; 1161 reg = <0x2000 0x1000>; 1162 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1163 }; 1164 1165 sec_jr2: jr@3000 { 1166 compatible = "fsl,sec-v4.0-job-ring"; 1167 reg = <0x3000 0x1000>; 1168 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1169 }; 1170 }; 1171 1172 i2c1: i2c@30a20000 { 1173 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 reg = <0x30a20000 0x10000>; 1177 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 1179 status = "disabled"; 1180 }; 1181 1182 i2c2: i2c@30a30000 { 1183 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 reg = <0x30a30000 0x10000>; 1187 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 1189 status = "disabled"; 1190 }; 1191 1192 i2c3: i2c@30a40000 { 1193 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 reg = <0x30a40000 0x10000>; 1197 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 1199 status = "disabled"; 1200 }; 1201 1202 i2c4: i2c@30a50000 { 1203 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 reg = <0x30a50000 0x10000>; 1207 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1208 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 1209 status = "disabled"; 1210 }; 1211 1212 uart4: serial@30a60000 { 1213 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1214 reg = <0x30a60000 0x10000>; 1215 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 1217 <&clk IMX8MP_CLK_UART4_ROOT>; 1218 clock-names = "ipg", "per"; 1219 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1220 dma-names = "rx", "tx"; 1221 status = "disabled"; 1222 }; 1223 1224 mu: mailbox@30aa0000 { 1225 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1226 reg = <0x30aa0000 0x10000>; 1227 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 1229 #mbox-cells = <2>; 1230 }; 1231 1232 mu2: mailbox@30e60000 { 1233 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1234 reg = <0x30e60000 0x10000>; 1235 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1236 #mbox-cells = <2>; 1237 status = "disabled"; 1238 }; 1239 1240 i2c5: i2c@30ad0000 { 1241 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 reg = <0x30ad0000 0x10000>; 1245 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1247 status = "disabled"; 1248 }; 1249 1250 i2c6: i2c@30ae0000 { 1251 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 reg = <0x30ae0000 0x10000>; 1255 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1256 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1257 status = "disabled"; 1258 }; 1259 1260 usdhc1: mmc@30b40000 { 1261 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1262 reg = <0x30b40000 0x10000>; 1263 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&clk IMX8MP_CLK_DUMMY>, 1265 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1266 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1267 clock-names = "ipg", "ahb", "per"; 1268 fsl,tuning-start-tap = <20>; 1269 fsl,tuning-step = <2>; 1270 bus-width = <4>; 1271 status = "disabled"; 1272 }; 1273 1274 usdhc2: mmc@30b50000 { 1275 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1276 reg = <0x30b50000 0x10000>; 1277 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1278 clocks = <&clk IMX8MP_CLK_DUMMY>, 1279 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1280 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1281 clock-names = "ipg", "ahb", "per"; 1282 fsl,tuning-start-tap = <20>; 1283 fsl,tuning-step = <2>; 1284 bus-width = <4>; 1285 status = "disabled"; 1286 }; 1287 1288 usdhc3: mmc@30b60000 { 1289 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1290 reg = <0x30b60000 0x10000>; 1291 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&clk IMX8MP_CLK_DUMMY>, 1293 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1294 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1295 clock-names = "ipg", "ahb", "per"; 1296 fsl,tuning-start-tap = <20>; 1297 fsl,tuning-step = <2>; 1298 bus-width = <4>; 1299 status = "disabled"; 1300 }; 1301 1302 flexspi: spi@30bb0000 { 1303 compatible = "nxp,imx8mp-fspi"; 1304 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1305 reg-names = "fspi_base", "fspi_mmap"; 1306 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1307 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1308 <&clk IMX8MP_CLK_QSPI_ROOT>; 1309 clock-names = "fspi_en", "fspi"; 1310 assigned-clock-rates = <80000000>; 1311 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 status = "disabled"; 1315 }; 1316 1317 sdma1: dma-controller@30bd0000 { 1318 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1319 reg = <0x30bd0000 0x10000>; 1320 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1322 <&clk IMX8MP_CLK_AHB>; 1323 clock-names = "ipg", "ahb"; 1324 #dma-cells = <3>; 1325 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1326 }; 1327 1328 fec: ethernet@30be0000 { 1329 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1330 reg = <0x30be0000 0x10000>; 1331 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1336 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1337 <&clk IMX8MP_CLK_ENET_TIMER>, 1338 <&clk IMX8MP_CLK_ENET_REF>, 1339 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1340 clock-names = "ipg", "ahb", "ptp", 1341 "enet_clk_ref", "enet_out"; 1342 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1343 <&clk IMX8MP_CLK_ENET_TIMER>, 1344 <&clk IMX8MP_CLK_ENET_REF>, 1345 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1346 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1347 <&clk IMX8MP_SYS_PLL2_100M>, 1348 <&clk IMX8MP_SYS_PLL2_125M>, 1349 <&clk IMX8MP_SYS_PLL2_50M>; 1350 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1351 fsl,num-tx-queues = <3>; 1352 fsl,num-rx-queues = <3>; 1353 nvmem-cells = <ð_mac1>; 1354 nvmem-cell-names = "mac-address"; 1355 fsl,stop-mode = <&gpr 0x10 3>; 1356 status = "disabled"; 1357 }; 1358 1359 eqos: ethernet@30bf0000 { 1360 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1361 reg = <0x30bf0000 0x10000>; 1362 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1364 interrupt-names = "macirq", "eth_wake_irq"; 1365 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1366 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1367 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1368 <&clk IMX8MP_CLK_ENET_QOS>; 1369 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1370 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1371 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1372 <&clk IMX8MP_CLK_ENET_QOS>; 1373 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1374 <&clk IMX8MP_SYS_PLL2_100M>, 1375 <&clk IMX8MP_SYS_PLL2_125M>; 1376 assigned-clock-rates = <0>, <100000000>, <125000000>; 1377 nvmem-cells = <ð_mac2>; 1378 nvmem-cell-names = "mac-address"; 1379 intf_mode = <&gpr 0x4>; 1380 status = "disabled"; 1381 }; 1382 }; 1383 1384 aips5: bus@30c00000 { 1385 compatible = "fsl,aips-bus", "simple-bus"; 1386 reg = <0x30c00000 0x400000>; 1387 #address-cells = <1>; 1388 #size-cells = <1>; 1389 ranges; 1390 1391 spba-bus@30c00000 { 1392 compatible = "fsl,spba-bus", "simple-bus"; 1393 reg = <0x30c00000 0x100000>; 1394 #address-cells = <1>; 1395 #size-cells = <1>; 1396 ranges; 1397 1398 sai1: sai@30c10000 { 1399 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1400 reg = <0x30c10000 0x10000>; 1401 #sound-dai-cells = <0>; 1402 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, 1403 <&clk IMX8MP_CLK_DUMMY>, 1404 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, 1405 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, 1406 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; 1407 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1408 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 1409 dma-names = "rx", "tx"; 1410 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1411 status = "disabled"; 1412 }; 1413 1414 sai2: sai@30c20000 { 1415 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1416 reg = <0x30c20000 0x10000>; 1417 #sound-dai-cells = <0>; 1418 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, 1419 <&clk IMX8MP_CLK_DUMMY>, 1420 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, 1421 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, 1422 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; 1423 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1424 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 1425 dma-names = "rx", "tx"; 1426 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1427 status = "disabled"; 1428 }; 1429 1430 sai3: sai@30c30000 { 1431 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1432 reg = <0x30c30000 0x10000>; 1433 #sound-dai-cells = <0>; 1434 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 1435 <&clk IMX8MP_CLK_DUMMY>, 1436 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 1437 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, 1438 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; 1439 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1440 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 1441 dma-names = "rx", "tx"; 1442 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1443 status = "disabled"; 1444 }; 1445 1446 sai5: sai@30c50000 { 1447 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1448 reg = <0x30c50000 0x10000>; 1449 #sound-dai-cells = <0>; 1450 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, 1451 <&clk IMX8MP_CLK_DUMMY>, 1452 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, 1453 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, 1454 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; 1455 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1456 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 1457 dma-names = "rx", "tx"; 1458 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1459 status = "disabled"; 1460 }; 1461 1462 sai6: sai@30c60000 { 1463 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1464 reg = <0x30c60000 0x10000>; 1465 #sound-dai-cells = <0>; 1466 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, 1467 <&clk IMX8MP_CLK_DUMMY>, 1468 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, 1469 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, 1470 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; 1471 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1472 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 1473 dma-names = "rx", "tx"; 1474 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1475 status = "disabled"; 1476 }; 1477 1478 sai7: sai@30c80000 { 1479 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1480 reg = <0x30c80000 0x10000>; 1481 #sound-dai-cells = <0>; 1482 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, 1483 <&clk IMX8MP_CLK_DUMMY>, 1484 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, 1485 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, 1486 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; 1487 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1488 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 1489 dma-names = "rx", "tx"; 1490 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1491 status = "disabled"; 1492 }; 1493 1494 easrc: easrc@30c90000 { 1495 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; 1496 reg = <0x30c90000 0x10000>; 1497 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1498 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; 1499 clock-names = "mem"; 1500 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 1501 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 1502 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 1503 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 1504 dma-names = "ctx0_rx", "ctx0_tx", 1505 "ctx1_rx", "ctx1_tx", 1506 "ctx2_rx", "ctx2_tx", 1507 "ctx3_rx", "ctx3_tx"; 1508 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 1509 fsl,asrc-rate = <8000>; 1510 fsl,asrc-format = <2>; 1511 status = "disabled"; 1512 }; 1513 1514 micfil: audio-controller@30ca0000 { 1515 compatible = "fsl,imx8mp-micfil"; 1516 reg = <0x30ca0000 0x10000>; 1517 #sound-dai-cells = <0>; 1518 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1522 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, 1523 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, 1524 <&clk IMX8MP_AUDIO_PLL1_OUT>, 1525 <&clk IMX8MP_AUDIO_PLL2_OUT>, 1526 <&clk IMX8MP_CLK_EXT3>; 1527 clock-names = "ipg_clk", "ipg_clk_app", 1528 "pll8k", "pll11k", "clkext3"; 1529 dmas = <&sdma2 24 25 0x80000000>; 1530 dma-names = "rx"; 1531 status = "disabled"; 1532 }; 1533 1534 aud2htx: aud2htx@30cb0000 { 1535 compatible = "fsl,imx8mp-aud2htx"; 1536 reg = <0x30cb0000 0x10000>; 1537 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1538 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; 1539 clock-names = "bus"; 1540 dmas = <&sdma2 26 2 0>; 1541 dma-names = "tx"; 1542 status = "disabled"; 1543 }; 1544 1545 xcvr: xcvr@30cc0000 { 1546 compatible = "fsl,imx8mp-xcvr"; 1547 reg = <0x30cc0000 0x800>, 1548 <0x30cc0800 0x400>, 1549 <0x30cc0c00 0x080>, 1550 <0x30cc0e00 0x080>; 1551 reg-names = "ram", "regs", "rxfifo", 1552 "txfifo"; 1553 interrupts = /* XCVR IRQ 0 */ 1554 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1555 /* XCVR IRQ 1 */ 1556 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1557 /* XCVR PHY - SPDIF wakeup IRQ */ 1558 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1559 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>, 1560 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>, 1561 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, 1562 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; 1563 clock-names = "ipg", "phy", "spba", "pll_ipg"; 1564 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; 1565 dma-names = "rx", "tx"; 1566 resets = <&audio_blk_ctrl 0>; 1567 status = "disabled"; 1568 }; 1569 }; 1570 1571 sdma3: dma-controller@30e00000 { 1572 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1573 reg = <0x30e00000 0x10000>; 1574 #dma-cells = <3>; 1575 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, 1576 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1577 clock-names = "ipg", "ahb"; 1578 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1579 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1580 }; 1581 1582 sdma2: dma-controller@30e10000 { 1583 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1584 reg = <0x30e10000 0x10000>; 1585 #dma-cells = <3>; 1586 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, 1587 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1588 clock-names = "ipg", "ahb"; 1589 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1590 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1591 }; 1592 1593 audio_blk_ctrl: clock-controller@30e20000 { 1594 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1595 reg = <0x30e20000 0x10000>; 1596 #clock-cells = <1>; 1597 #reset-cells = <1>; 1598 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1599 <&clk IMX8MP_CLK_SAI1>, 1600 <&clk IMX8MP_CLK_SAI2>, 1601 <&clk IMX8MP_CLK_SAI3>, 1602 <&clk IMX8MP_CLK_SAI5>, 1603 <&clk IMX8MP_CLK_SAI6>, 1604 <&clk IMX8MP_CLK_SAI7>; 1605 clock-names = "ahb", 1606 "sai1", "sai2", "sai3", 1607 "sai5", "sai6", "sai7"; 1608 power-domains = <&pgc_audio>; 1609 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, 1610 <&clk IMX8MP_AUDIO_PLL2>; 1611 assigned-clock-rates = <393216000>, <361267200>; 1612 }; 1613 }; 1614 1615 noc: interconnect@32700000 { 1616 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1617 reg = <0x32700000 0x100000>; 1618 clocks = <&clk IMX8MP_CLK_NOC>; 1619 #interconnect-cells = <1>; 1620 operating-points-v2 = <&noc_opp_table>; 1621 1622 noc_opp_table: opp-table { 1623 compatible = "operating-points-v2"; 1624 1625 opp-200000000 { 1626 opp-hz = /bits/ 64 <200000000>; 1627 }; 1628 1629 opp-1000000000 { 1630 opp-hz = /bits/ 64 <1000000000>; 1631 }; 1632 }; 1633 }; 1634 1635 aips4: bus@32c00000 { 1636 compatible = "fsl,aips-bus", "simple-bus"; 1637 reg = <0x32c00000 0x400000>; 1638 #address-cells = <1>; 1639 #size-cells = <1>; 1640 ranges; 1641 1642 isi_0: isi@32e00000 { 1643 compatible = "fsl,imx8mp-isi"; 1644 reg = <0x32e00000 0x4000>; 1645 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1647 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1648 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1649 clock-names = "axi", "apb"; 1650 fsl,blk-ctrl = <&media_blk_ctrl>; 1651 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; 1652 status = "disabled"; 1653 1654 ports { 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 1658 port@0 { 1659 reg = <0>; 1660 1661 isi_in_0: endpoint { 1662 remote-endpoint = <&mipi_csi_0_out>; 1663 }; 1664 }; 1665 1666 port@1 { 1667 reg = <1>; 1668 1669 isi_in_1: endpoint { 1670 remote-endpoint = <&mipi_csi_1_out>; 1671 }; 1672 }; 1673 }; 1674 }; 1675 1676 dewarp: dwe@32e30000 { 1677 compatible = "nxp,imx8mp-dw100"; 1678 reg = <0x32e30000 0x10000>; 1679 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1680 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1681 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1682 clock-names = "axi", "ahb"; 1683 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; 1684 }; 1685 1686 mipi_csi_0: csi@32e40000 { 1687 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1688 reg = <0x32e40000 0x10000>; 1689 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1690 clock-frequency = <266000000>; 1691 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1692 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1693 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1694 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1695 clock-names = "pclk", "wrap", "phy", "axi"; 1696 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, 1697 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1698 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1699 <&clk IMX8MP_CLK_24M>; 1700 assigned-clock-rates = <266000000>; 1701 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1702 status = "disabled"; 1703 1704 ports { 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 1708 port@0 { 1709 reg = <0>; 1710 }; 1711 1712 port@1 { 1713 reg = <1>; 1714 1715 mipi_csi_0_out: endpoint { 1716 remote-endpoint = <&isi_in_0>; 1717 }; 1718 }; 1719 }; 1720 }; 1721 1722 mipi_csi_1: csi@32e50000 { 1723 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1724 reg = <0x32e50000 0x10000>; 1725 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1726 clock-frequency = <266000000>; 1727 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1728 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1729 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1730 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1731 clock-names = "pclk", "wrap", "phy", "axi"; 1732 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, 1733 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1734 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1735 <&clk IMX8MP_CLK_24M>; 1736 assigned-clock-rates = <266000000>; 1737 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1738 status = "disabled"; 1739 1740 ports { 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 1744 port@0 { 1745 reg = <0>; 1746 }; 1747 1748 port@1 { 1749 reg = <1>; 1750 1751 mipi_csi_1_out: endpoint { 1752 remote-endpoint = <&isi_in_1>; 1753 }; 1754 }; 1755 }; 1756 }; 1757 1758 mipi_dsi: dsi@32e60000 { 1759 compatible = "fsl,imx8mp-mipi-dsim"; 1760 reg = <0x32e60000 0x400>; 1761 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1762 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1763 clock-names = "bus_clk", "sclk_mipi"; 1764 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1765 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1766 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1767 <&clk IMX8MP_CLK_24M>; 1768 assigned-clock-rates = <200000000>, <24000000>; 1769 samsung,pll-clock-frequency = <24000000>; 1770 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1771 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1772 status = "disabled"; 1773 1774 ports { 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 1778 port@0 { 1779 reg = <0>; 1780 1781 dsim_from_lcdif1: endpoint { 1782 remote-endpoint = <&lcdif1_to_dsim>; 1783 }; 1784 }; 1785 1786 port@1 { 1787 reg = <1>; 1788 1789 mipi_dsi_out: endpoint { 1790 }; 1791 }; 1792 }; 1793 }; 1794 1795 lcdif1: display-controller@32e80000 { 1796 compatible = "fsl,imx8mp-lcdif"; 1797 reg = <0x32e80000 0x10000>; 1798 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1799 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1800 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1801 clock-names = "pix", "axi", "disp_axi"; 1802 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1803 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1804 status = "disabled"; 1805 1806 port { 1807 lcdif1_to_dsim: endpoint { 1808 remote-endpoint = <&dsim_from_lcdif1>; 1809 }; 1810 }; 1811 }; 1812 1813 lcdif2: display-controller@32e90000 { 1814 compatible = "fsl,imx8mp-lcdif"; 1815 reg = <0x32e90000 0x10000>; 1816 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1817 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1818 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1819 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1820 clock-names = "pix", "axi", "disp_axi"; 1821 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1822 status = "disabled"; 1823 1824 port { 1825 lcdif2_to_ldb: endpoint { 1826 remote-endpoint = <&ldb_from_lcdif2>; 1827 }; 1828 }; 1829 }; 1830 1831 media_blk_ctrl: blk-ctrl@32ec0000 { 1832 compatible = "fsl,imx8mp-media-blk-ctrl", 1833 "syscon"; 1834 reg = <0x32ec0000 0x10000>; 1835 #address-cells = <1>; 1836 #size-cells = <1>; 1837 power-domains = <&pgc_mediamix>, 1838 <&pgc_mipi_phy1>, 1839 <&pgc_mipi_phy1>, 1840 <&pgc_mediamix>, 1841 <&pgc_mediamix>, 1842 <&pgc_mipi_phy2>, 1843 <&pgc_mediamix>, 1844 <&pgc_ispdwp>, 1845 <&pgc_ispdwp>, 1846 <&pgc_mipi_phy2>; 1847 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1848 "lcdif1", "isi", "mipi-csi2", 1849 "lcdif2", "isp", "dwe", 1850 "mipi-dsi2"; 1851 interconnects = 1852 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1853 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1854 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1855 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1856 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1857 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1858 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1859 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1860 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1861 "isi1", "isi2", "isp0", "isp1", 1862 "dwe"; 1863 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1864 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1865 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1866 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1867 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1868 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1869 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1870 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1871 clock-names = "apb", "axi", "cam1", "cam2", 1872 "disp1", "disp2", "isp", "phy"; 1873 1874 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1875 <&clk IMX8MP_CLK_MEDIA_APB>, 1876 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1877 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1878 <&clk IMX8MP_VIDEO_PLL1>; 1879 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1880 <&clk IMX8MP_SYS_PLL1_800M>, 1881 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1882 <&clk IMX8MP_VIDEO_PLL1_OUT>; 1883 assigned-clock-rates = <500000000>, <200000000>, 1884 <0>, <0>, <1039500000>; 1885 #power-domain-cells = <1>; 1886 1887 lvds_bridge: bridge@5c { 1888 compatible = "fsl,imx8mp-ldb"; 1889 reg = <0x5c 0x4>, <0x128 0x4>; 1890 reg-names = "ldb", "lvds"; 1891 clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; 1892 clock-names = "ldb"; 1893 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1894 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1895 status = "disabled"; 1896 1897 ports { 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 1901 port@0 { 1902 reg = <0>; 1903 1904 ldb_from_lcdif2: endpoint { 1905 remote-endpoint = <&lcdif2_to_ldb>; 1906 }; 1907 }; 1908 1909 port@1 { 1910 reg = <1>; 1911 1912 ldb_lvds_ch0: endpoint { 1913 }; 1914 }; 1915 1916 port@2 { 1917 reg = <2>; 1918 1919 ldb_lvds_ch1: endpoint { 1920 }; 1921 }; 1922 }; 1923 }; 1924 }; 1925 1926 pcie_phy: pcie-phy@32f00000 { 1927 compatible = "fsl,imx8mp-pcie-phy"; 1928 reg = <0x32f00000 0x10000>; 1929 resets = <&src IMX8MP_RESET_PCIEPHY>, 1930 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1931 reset-names = "pciephy", "perst"; 1932 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1933 #phy-cells = <0>; 1934 status = "disabled"; 1935 }; 1936 1937 hsio_blk_ctrl: blk-ctrl@32f10000 { 1938 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1939 reg = <0x32f10000 0x24>; 1940 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1941 <&clk IMX8MP_CLK_PCIE_ROOT>; 1942 clock-names = "usb", "pcie"; 1943 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1944 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1945 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1946 power-domain-names = "bus", "usb", "usb-phy1", 1947 "usb-phy2", "pcie", "pcie-phy"; 1948 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1949 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1950 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1951 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1952 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1953 #power-domain-cells = <1>; 1954 #clock-cells = <0>; 1955 }; 1956 1957 hdmi_blk_ctrl: blk-ctrl@32fc0000 { 1958 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; 1959 reg = <0x32fc0000 0x1000>; 1960 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 1961 <&clk IMX8MP_CLK_HDMI_ROOT>, 1962 <&clk IMX8MP_CLK_HDMI_REF_266M>, 1963 <&clk IMX8MP_CLK_HDMI_24M>, 1964 <&clk IMX8MP_CLK_HDMI_FDCC_TST>; 1965 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; 1966 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, 1967 <&pgc_hdmimix>, <&pgc_hdmimix>, 1968 <&pgc_hdmimix>, <&pgc_hdmimix>, 1969 <&pgc_hdmimix>, <&pgc_hdmi_phy>, 1970 <&pgc_hdmimix>, <&pgc_hdmimix>; 1971 power-domain-names = "bus", "irqsteer", "lcdif", 1972 "pai", "pvi", "trng", 1973 "hdmi-tx", "hdmi-tx-phy", 1974 "hdcp", "hrv"; 1975 #power-domain-cells = <1>; 1976 }; 1977 1978 irqsteer_hdmi: interrupt-controller@32fc2000 { 1979 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer"; 1980 reg = <0x32fc2000 0x1000>; 1981 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1982 interrupt-controller; 1983 #interrupt-cells = <1>; 1984 fsl,channel = <1>; 1985 fsl,num-irqs = <64>; 1986 clocks = <&clk IMX8MP_CLK_HDMI_APB>; 1987 clock-names = "ipg"; 1988 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; 1989 }; 1990 1991 hdmi_pvi: display-bridge@32fc4000 { 1992 compatible = "fsl,imx8mp-hdmi-pvi"; 1993 reg = <0x32fc4000 0x1000>; 1994 interrupt-parent = <&irqsteer_hdmi>; 1995 interrupts = <12>; 1996 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; 1997 status = "disabled"; 1998 1999 ports { 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 2003 port@0 { 2004 reg = <0>; 2005 pvi_from_lcdif3: endpoint { 2006 remote-endpoint = <&lcdif3_to_pvi>; 2007 }; 2008 }; 2009 2010 port@1 { 2011 reg = <1>; 2012 pvi_to_hdmi_tx: endpoint { 2013 remote-endpoint = <&hdmi_tx_from_pvi>; 2014 }; 2015 }; 2016 }; 2017 }; 2018 2019 lcdif3: display-controller@32fc6000 { 2020 compatible = "fsl,imx8mp-lcdif"; 2021 reg = <0x32fc6000 0x1000>; 2022 interrupt-parent = <&irqsteer_hdmi>; 2023 interrupts = <8>; 2024 clocks = <&hdmi_tx_phy>, 2025 <&clk IMX8MP_CLK_HDMI_APB>, 2026 <&clk IMX8MP_CLK_HDMI_ROOT>; 2027 clock-names = "pix", "axi", "disp_axi"; 2028 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; 2029 status = "disabled"; 2030 2031 port { 2032 lcdif3_to_pvi: endpoint { 2033 remote-endpoint = <&pvi_from_lcdif3>; 2034 }; 2035 }; 2036 }; 2037 2038 hdmi_tx: hdmi@32fd8000 { 2039 compatible = "fsl,imx8mp-hdmi-tx"; 2040 reg = <0x32fd8000 0x7eff>; 2041 interrupt-parent = <&irqsteer_hdmi>; 2042 interrupts = <0>; 2043 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2044 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2045 <&clk IMX8MP_CLK_32K>, 2046 <&hdmi_tx_phy>; 2047 clock-names = "iahb", "isfr", "cec", "pix"; 2048 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; 2049 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; 2050 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; 2051 reg-io-width = <1>; 2052 status = "disabled"; 2053 2054 ports { 2055 #address-cells = <1>; 2056 #size-cells = <0>; 2057 2058 port@0 { 2059 reg = <0>; 2060 2061 hdmi_tx_from_pvi: endpoint { 2062 remote-endpoint = <&pvi_to_hdmi_tx>; 2063 }; 2064 }; 2065 2066 port@1 { 2067 reg = <1>; 2068 /* Point endpoint to the HDMI connector */ 2069 }; 2070 }; 2071 }; 2072 2073 hdmi_tx_phy: phy@32fdff00 { 2074 compatible = "fsl,imx8mp-hdmi-phy"; 2075 reg = <0x32fdff00 0x100>; 2076 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2077 <&clk IMX8MP_CLK_HDMI_24M>; 2078 clock-names = "apb", "ref"; 2079 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; 2080 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2081 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; 2082 #clock-cells = <0>; 2083 #phy-cells = <0>; 2084 status = "disabled"; 2085 }; 2086 }; 2087 2088 pcie: pcie@33800000 { 2089 compatible = "fsl,imx8mp-pcie"; 2090 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 2091 reg-names = "dbi", "config"; 2092 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2093 <&clk IMX8MP_CLK_HSIO_AXI>, 2094 <&clk IMX8MP_CLK_PCIE_ROOT>; 2095 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2096 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2097 assigned-clock-rates = <10000000>; 2098 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2099 #address-cells = <3>; 2100 #size-cells = <2>; 2101 device_type = "pci"; 2102 bus-range = <0x00 0xff>; 2103 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 2104 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 2105 num-lanes = <1>; 2106 num-viewport = <4>; 2107 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2108 interrupt-names = "msi"; 2109 #interrupt-cells = <1>; 2110 interrupt-map-mask = <0 0 0 0x7>; 2111 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2112 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2113 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2114 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2115 fsl,max-link-speed = <3>; 2116 linux,pci-domain = <0>; 2117 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2118 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2119 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2120 reset-names = "apps", "turnoff"; 2121 phys = <&pcie_phy>; 2122 phy-names = "pcie-phy"; 2123 status = "disabled"; 2124 }; 2125 2126 pcie_ep: pcie-ep@33800000 { 2127 compatible = "fsl,imx8mp-pcie-ep"; 2128 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 2129 reg-names = "dbi", "addr_space"; 2130 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2131 <&clk IMX8MP_CLK_HSIO_AXI>, 2132 <&clk IMX8MP_CLK_PCIE_ROOT>; 2133 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2134 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2135 assigned-clock-rates = <10000000>; 2136 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2137 num-lanes = <1>; 2138 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 2139 interrupt-names = "dma"; 2140 fsl,max-link-speed = <3>; 2141 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2142 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2143 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2144 reset-names = "apps", "turnoff"; 2145 phys = <&pcie_phy>; 2146 phy-names = "pcie-phy"; 2147 num-ib-windows = <4>; 2148 num-ob-windows = <4>; 2149 status = "disabled"; 2150 }; 2151 2152 gpu3d: gpu@38000000 { 2153 compatible = "vivante,gc"; 2154 reg = <0x38000000 0x8000>; 2155 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2156 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 2157 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 2158 <&clk IMX8MP_CLK_GPU_ROOT>, 2159 <&clk IMX8MP_CLK_GPU_AHB>; 2160 clock-names = "core", "shader", "bus", "reg"; 2161 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 2162 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 2163 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 2164 <&clk IMX8MP_SYS_PLL1_800M>; 2165 assigned-clock-rates = <800000000>, <800000000>; 2166 power-domains = <&pgc_gpu3d>; 2167 }; 2168 2169 gpu2d: gpu@38008000 { 2170 compatible = "vivante,gc"; 2171 reg = <0x38008000 0x8000>; 2172 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2173 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 2174 <&clk IMX8MP_CLK_GPU_ROOT>, 2175 <&clk IMX8MP_CLK_GPU_AHB>; 2176 clock-names = "core", "bus", "reg"; 2177 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 2178 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 2179 assigned-clock-rates = <800000000>; 2180 power-domains = <&pgc_gpu2d>; 2181 }; 2182 2183 vpu_g1: video-codec@38300000 { 2184 compatible = "nxp,imx8mm-vpu-g1"; 2185 reg = <0x38300000 0x10000>; 2186 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2187 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 2188 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 2189 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2190 assigned-clock-rates = <600000000>; 2191 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 2192 }; 2193 2194 vpu_g2: video-codec@38310000 { 2195 compatible = "nxp,imx8mq-vpu-g2"; 2196 reg = <0x38310000 0x10000>; 2197 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2198 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 2199 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 2200 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 2201 assigned-clock-rates = <500000000>; 2202 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 2203 }; 2204 2205 vpumix_blk_ctrl: blk-ctrl@38330000 { 2206 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 2207 reg = <0x38330000 0x100>; 2208 #power-domain-cells = <1>; 2209 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 2210 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 2211 power-domain-names = "bus", "g1", "g2", "vc8000e"; 2212 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 2213 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 2214 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 2215 clock-names = "g1", "g2", "vc8000e"; 2216 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 2217 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2218 assigned-clock-rates = <600000000>, <600000000>; 2219 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 2220 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 2221 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 2222 interconnect-names = "g1", "g2", "vc8000e"; 2223 }; 2224 2225 npu: npu@38500000 { 2226 compatible = "vivante,gc"; 2227 reg = <0x38500000 0x200000>; 2228 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2229 clocks = <&clk IMX8MP_CLK_NPU_ROOT>, 2230 <&clk IMX8MP_CLK_NPU_ROOT>, 2231 <&clk IMX8MP_CLK_ML_AXI>, 2232 <&clk IMX8MP_CLK_ML_AHB>; 2233 clock-names = "core", "shader", "bus", "reg"; 2234 power-domains = <&pgc_mlmix>; 2235 }; 2236 2237 gic: interrupt-controller@38800000 { 2238 compatible = "arm,gic-v3"; 2239 reg = <0x38800000 0x10000>, 2240 <0x38880000 0xc0000>; 2241 #interrupt-cells = <3>; 2242 interrupt-controller; 2243 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2244 interrupt-parent = <&gic>; 2245 }; 2246 2247 edacmc: memory-controller@3d400000 { 2248 compatible = "snps,ddrc-3.80a"; 2249 reg = <0x3d400000 0x400000>; 2250 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2251 }; 2252 2253 ddr-pmu@3d800000 { 2254 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 2255 reg = <0x3d800000 0x400000>; 2256 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2257 }; 2258 2259 usb3_phy0: usb-phy@381f0040 { 2260 compatible = "fsl,imx8mp-usb-phy"; 2261 reg = <0x381f0040 0x40>; 2262 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2263 clock-names = "phy"; 2264 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2265 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2266 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 2267 #phy-cells = <0>; 2268 status = "disabled"; 2269 }; 2270 2271 usb3_0: usb@32f10100 { 2272 compatible = "fsl,imx8mp-dwc3"; 2273 reg = <0x32f10100 0x8>, 2274 <0x381f0000 0x20>; 2275 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2276 <&clk IMX8MP_CLK_USB_SUSP>; 2277 clock-names = "hsio", "suspend"; 2278 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2279 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2280 #address-cells = <1>; 2281 #size-cells = <1>; 2282 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2283 ranges; 2284 status = "disabled"; 2285 2286 usb_dwc3_0: usb@38100000 { 2287 compatible = "snps,dwc3"; 2288 reg = <0x38100000 0x10000>; 2289 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2290 <&clk IMX8MP_CLK_USB_CORE_REF>, 2291 <&clk IMX8MP_CLK_USB_SUSP>; 2292 clock-names = "bus_early", "ref", "suspend"; 2293 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2294 phys = <&usb3_phy0>, <&usb3_phy0>; 2295 phy-names = "usb2-phy", "usb3-phy"; 2296 snps,gfladj-refclk-lpm-sel-quirk; 2297 snps,parkmode-disable-ss-quirk; 2298 }; 2299 2300 }; 2301 2302 usb3_phy1: usb-phy@382f0040 { 2303 compatible = "fsl,imx8mp-usb-phy"; 2304 reg = <0x382f0040 0x40>; 2305 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2306 clock-names = "phy"; 2307 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2308 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2309 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 2310 #phy-cells = <0>; 2311 status = "disabled"; 2312 }; 2313 2314 usb3_1: usb@32f10108 { 2315 compatible = "fsl,imx8mp-dwc3"; 2316 reg = <0x32f10108 0x8>, 2317 <0x382f0000 0x20>; 2318 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2319 <&clk IMX8MP_CLK_USB_SUSP>; 2320 clock-names = "hsio", "suspend"; 2321 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2322 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2323 #address-cells = <1>; 2324 #size-cells = <1>; 2325 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2326 ranges; 2327 status = "disabled"; 2328 2329 usb_dwc3_1: usb@38200000 { 2330 compatible = "snps,dwc3"; 2331 reg = <0x38200000 0x10000>; 2332 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2333 <&clk IMX8MP_CLK_USB_CORE_REF>, 2334 <&clk IMX8MP_CLK_USB_SUSP>; 2335 clock-names = "bus_early", "ref", "suspend"; 2336 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 2337 phys = <&usb3_phy1>, <&usb3_phy1>; 2338 phy-names = "usb2-phy", "usb3-phy"; 2339 snps,gfladj-refclk-lpm-sel-quirk; 2340 snps,parkmode-disable-ss-quirk; 2341 }; 2342 }; 2343 2344 dsp: dsp@3b6e8000 { 2345 compatible = "fsl,imx8mp-dsp"; 2346 reg = <0x3b6e8000 0x88000>; 2347 mbox-names = "txdb0", "txdb1", 2348 "rxdb0", "rxdb1"; 2349 mboxes = <&mu2 2 0>, <&mu2 2 1>, 2350 <&mu2 3 0>, <&mu2 3 1>; 2351 memory-region = <&dsp_reserved>; 2352 status = "disabled"; 2353 }; 2354 }; 2355}; 2356