1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mp.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart3; 13 }; 14 15 aliases { 16 /* Ethernet aliases to ensure correct MAC addresses */ 17 ethernet0 = &eqos; 18 ethernet1 = &fec; 19 rtc0 = &rtc_i2c; 20 rtc1 = &snvs_rtc; 21 }; 22 23 backlight: backlight { 24 compatible = "pwm-backlight"; 25 brightness-levels = <0 45 63 88 119 158 203 255>; 26 default-brightness-level = <4>; 27 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 28 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 31 power-supply = <®_3p3v>; 32 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 33 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; 34 status = "disabled"; 35 }; 36 37 backlight_mezzanine: backlight-mezzanine { 38 compatible = "pwm-backlight"; 39 brightness-levels = <0 45 63 88 119 158 203 255>; 40 default-brightness-level = <4>; 41 /* Verdin GPIO 4 (SODIMM 212) */ 42 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 43 /* Verdin PWM_2 (SODIMM 16) */ 44 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; 45 status = "disabled"; 46 }; 47 48 connector { 49 compatible = "gpio-usb-b-connector", "usb-b-connector"; 50 id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 51 label = "Type-C"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pinctrl_usb_1_id>; 54 self-powered; 55 type = "micro"; 56 vbus-supply = <®_usb1_vbus>; 57 58 port { 59 usb_dr_connector: endpoint { 60 remote-endpoint = <&usb3_dwc>; 61 }; 62 }; 63 }; 64 65 gpio-keys { 66 compatible = "gpio-keys"; 67 pinctrl-names = "default"; 68 pinctrl-0 = <&pinctrl_gpio_keys>; 69 70 key-wakeup { 71 debounce-interval = <10>; 72 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 73 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 74 label = "Wake-Up"; 75 linux,code = <KEY_WAKEUP>; 76 wakeup-source; 77 }; 78 }; 79 80 /* Carrier Board Supplies */ 81 reg_1p8v: regulator-1p8v { 82 compatible = "regulator-fixed"; 83 regulator-max-microvolt = <1800000>; 84 regulator-min-microvolt = <1800000>; 85 regulator-name = "+V1.8_SW"; 86 }; 87 88 reg_3p3v: regulator-3p3v { 89 compatible = "regulator-fixed"; 90 regulator-max-microvolt = <3300000>; 91 regulator-min-microvolt = <3300000>; 92 regulator-name = "+V3.3_SW"; 93 }; 94 95 reg_5p0v: regulator-5p0v { 96 compatible = "regulator-fixed"; 97 regulator-max-microvolt = <5000000>; 98 regulator-min-microvolt = <5000000>; 99 regulator-name = "+V5_SW"; 100 }; 101 102 /* Non PMIC On-module Supplies */ 103 reg_module_eth1phy: regulator-module-eth1phy { 104 compatible = "regulator-fixed"; 105 enable-active-high; 106 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 107 off-on-delay-us = <500000>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_reg_eth>; 110 regulator-always-on; 111 regulator-boot-on; 112 regulator-max-microvolt = <3300000>; 113 regulator-min-microvolt = <3300000>; 114 regulator-name = "On-module +V3.3_ETH"; 115 startup-delay-us = <200000>; 116 vin-supply = <®_vdd_3v3>; 117 }; 118 119 /* 120 * By default we enable CTRL_SLEEP_MOCI#, this is required to have 121 * peripherals on the carrier board powered. 122 * If more granularity or power saving is required this can be disabled 123 * in the carrier board device tree files. 124 */ 125 reg_force_sleep_moci: regulator-force-sleep-moci { 126 compatible = "regulator-fixed"; 127 enable-active-high; 128 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 129 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 130 regulator-always-on; 131 regulator-boot-on; 132 regulator-name = "CTRL_SLEEP_MOCI#"; 133 }; 134 135 reg_usb1_vbus: regulator-usb1-vbus { 136 compatible = "regulator-fixed"; 137 enable-active-high; 138 /* Verdin USB_1_EN (SODIMM 155) */ 139 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_usb1_vbus>; 142 regulator-max-microvolt = <5000000>; 143 regulator-min-microvolt = <5000000>; 144 regulator-name = "USB_1_EN"; 145 }; 146 147 reg_usb2_vbus: regulator-usb2-vbus { 148 compatible = "regulator-fixed"; 149 enable-active-high; 150 /* Verdin USB_2_EN (SODIMM 185) */ 151 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_usb2_vbus>; 154 regulator-max-microvolt = <5000000>; 155 regulator-min-microvolt = <5000000>; 156 regulator-name = "USB_2_EN"; 157 }; 158 159 reg_usdhc2_vmmc: regulator-usdhc2 { 160 compatible = "regulator-fixed"; 161 enable-active-high; 162 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 163 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; 164 off-on-delay-us = <100000>; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 167 regulator-max-microvolt = <3300000>; 168 regulator-min-microvolt = <3300000>; 169 regulator-name = "+V3.3_SD"; 170 startup-delay-us = <2000>; 171 }; 172 173 reserved-memory { 174 #address-cells = <2>; 175 #size-cells = <2>; 176 ranges; 177 178 /* Use the kernel configuration settings instead */ 179 /delete-node/ linux,cma; 180 }; 181}; 182 183&A53_0 { 184 cpu-supply = <®_vdd_arm>; 185}; 186 187&A53_1 { 188 cpu-supply = <®_vdd_arm>; 189}; 190 191&A53_2 { 192 cpu-supply = <®_vdd_arm>; 193}; 194 195&A53_3 { 196 cpu-supply = <®_vdd_arm>; 197}; 198 199&cpu_alert0 { 200 temperature = <95000>; 201}; 202 203&cpu_crit0 { 204 temperature = <105000>; 205}; 206 207/* Verdin SPI_1 */ 208&ecspi1 { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_ecspi1>; 214}; 215 216/* Verdin ETH_1 (On-module PHY) */ 217&eqos { 218 phy-handle = <ðphy0>; 219 phy-mode = "rgmii-id"; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_eqos>; 222 snps,force_thresh_dma_mode; 223 snps,mtl-rx-config = <&mtl_rx_setup>; 224 snps,mtl-tx-config = <&mtl_tx_setup>; 225 226 mdio { 227 compatible = "snps,dwmac-mdio"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 ethphy0: ethernet-phy@7 { 232 compatible = "ethernet-phy-ieee802.3-c22"; 233 eee-broken-100tx; 234 eee-broken-1000t; 235 interrupt-parent = <&gpio1>; 236 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 237 micrel,led-mode = <0>; 238 reg = <7>; 239 }; 240 }; 241 242 mtl_rx_setup: rx-queues-config { 243 snps,rx-queues-to-use = <5>; 244 snps,rx-sched-sp; 245 246 queue0 { 247 snps,dcb-algorithm; 248 snps,priority = <0x1>; 249 snps,map-to-dma-channel = <0>; 250 }; 251 252 queue1 { 253 snps,dcb-algorithm; 254 snps,priority = <0x2>; 255 snps,map-to-dma-channel = <1>; 256 }; 257 258 queue2 { 259 snps,dcb-algorithm; 260 snps,priority = <0x4>; 261 snps,map-to-dma-channel = <2>; 262 }; 263 264 queue3 { 265 snps,dcb-algorithm; 266 snps,priority = <0x8>; 267 snps,map-to-dma-channel = <3>; 268 }; 269 270 queue4 { 271 snps,dcb-algorithm; 272 snps,priority = <0xf0>; 273 snps,map-to-dma-channel = <4>; 274 }; 275 }; 276 277 mtl_tx_setup: tx-queues-config { 278 snps,tx-queues-to-use = <5>; 279 snps,tx-sched-sp; 280 281 queue0 { 282 snps,dcb-algorithm; 283 snps,priority = <0x1>; 284 }; 285 286 queue1 { 287 snps,dcb-algorithm; 288 snps,priority = <0x2>; 289 }; 290 291 queue2 { 292 snps,dcb-algorithm; 293 snps,priority = <0x4>; 294 }; 295 296 queue3 { 297 snps,dcb-algorithm; 298 snps,priority = <0x8>; 299 }; 300 301 queue4 { 302 snps,dcb-algorithm; 303 snps,priority = <0xf0>; 304 }; 305 }; 306}; 307 308/* Verdin ETH_2_RGMII */ 309&fec { 310 fsl,magic-packet; 311 phy-handle = <ðphy1>; 312 phy-mode = "rgmii-id"; 313 pinctrl-names = "default", "sleep"; 314 pinctrl-0 = <&pinctrl_fec>; 315 pinctrl-1 = <&pinctrl_fec_sleep>; 316 317 mdio { 318 #address-cells = <1>; 319 #size-cells = <0>; 320 321 ethphy1: ethernet-phy@7 { 322 compatible = "ethernet-phy-ieee802.3-c22"; 323 interrupt-parent = <&gpio4>; 324 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 325 micrel,led-mode = <0>; 326 reg = <7>; 327 }; 328 }; 329}; 330 331/* Verdin CAN_1 */ 332&flexcan1 { 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_flexcan1>; 335 status = "disabled"; 336}; 337 338/* Verdin CAN_2 */ 339&flexcan2 { 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_flexcan2>; 342 status = "disabled"; 343}; 344 345/* Verdin QSPI_1 */ 346&flexspi { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_flexspi0>; 349}; 350 351&gpio1 { 352 gpio-line-names = "SODIMM_206", 353 "SODIMM_208", 354 "", 355 "", 356 "", 357 "SODIMM_210", 358 "SODIMM_212", 359 "SODIMM_216", 360 "SODIMM_218", 361 "", 362 "", 363 "SODIMM_16", 364 "SODIMM_155", 365 "SODIMM_157", 366 "SODIMM_185", 367 "SODIMM_91"; 368}; 369 370&gpio2 { 371 gpio-line-names = "", 372 "", 373 "", 374 "", 375 "", 376 "", 377 "SODIMM_143", 378 "SODIMM_141", 379 "", 380 "", 381 "SODIMM_161", 382 "", 383 "SODIMM_84", 384 "SODIMM_78", 385 "SODIMM_74", 386 "SODIMM_80", 387 "SODIMM_82", 388 "SODIMM_70", 389 "SODIMM_72"; 390}; 391 392&gpio3 { 393 gpio-line-names = "SODIMM_52", 394 "SODIMM_54", 395 "", 396 "", 397 "", 398 "", 399 "SODIMM_56", 400 "SODIMM_58", 401 "SODIMM_60", 402 "SODIMM_62", 403 "", 404 "", 405 "", 406 "", 407 "SODIMM_66", 408 "", 409 "SODIMM_64", 410 "", 411 "", 412 "SODIMM_34", 413 "SODIMM_19", 414 "", 415 "SODIMM_32", 416 "", 417 "", 418 "SODIMM_30", 419 "SODIMM_59", 420 "SODIMM_57", 421 "SODIMM_63", 422 "SODIMM_61"; 423}; 424 425&gpio4 { 426 gpio-line-names = "SODIMM_252", 427 "SODIMM_222", 428 "SODIMM_36", 429 "SODIMM_220", 430 "SODIMM_193", 431 "SODIMM_191", 432 "SODIMM_201", 433 "SODIMM_203", 434 "SODIMM_205", 435 "SODIMM_207", 436 "SODIMM_199", 437 "SODIMM_197", 438 "SODIMM_221", 439 "SODIMM_219", 440 "SODIMM_217", 441 "SODIMM_215", 442 "SODIMM_211", 443 "SODIMM_213", 444 "SODIMM_189", 445 "SODIMM_244", 446 "SODIMM_38", 447 "", 448 "SODIMM_76", 449 "SODIMM_135", 450 "SODIMM_133", 451 "SODIMM_17", 452 "SODIMM_24", 453 "SODIMM_26", 454 "SODIMM_21", 455 "SODIMM_256", 456 "SODIMM_48", 457 "SODIMM_44"; 458}; 459 460/* On-module I2C */ 461&i2c1 { 462 clock-frequency = <400000>; 463 pinctrl-names = "default", "gpio"; 464 pinctrl-0 = <&pinctrl_i2c1>; 465 pinctrl-1 = <&pinctrl_i2c1_gpio>; 466 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 467 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 468 status = "okay"; 469 470 pca9450: pmic@25 { 471 compatible = "nxp,pca9450c"; 472 interrupt-parent = <&gpio1>; 473 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 474 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&pinctrl_pmic>; 477 reg = <0x25>; 478 479 /* 480 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the 481 * I2C level shifter for the TLA2024 ADC behind this PMIC. 482 */ 483 484 regulators { 485 BUCK1 { 486 regulator-always-on; 487 regulator-boot-on; 488 regulator-max-microvolt = <1000000>; 489 regulator-min-microvolt = <720000>; 490 regulator-name = "On-module +VDD_SOC (BUCK1)"; 491 regulator-ramp-delay = <3125>; 492 }; 493 494 reg_vdd_arm: BUCK2 { 495 nxp,dvs-run-voltage = <950000>; 496 nxp,dvs-standby-voltage = <850000>; 497 regulator-always-on; 498 regulator-boot-on; 499 regulator-max-microvolt = <1025000>; 500 regulator-min-microvolt = <720000>; 501 regulator-name = "On-module +VDD_ARM (BUCK2)"; 502 regulator-ramp-delay = <3125>; 503 }; 504 505 reg_vdd_3v3: BUCK4 { 506 regulator-always-on; 507 regulator-boot-on; 508 regulator-max-microvolt = <3300000>; 509 regulator-min-microvolt = <3300000>; 510 regulator-name = "On-module +V3.3 (BUCK4)"; 511 }; 512 513 reg_vdd_1v8: BUCK5 { 514 regulator-always-on; 515 regulator-boot-on; 516 regulator-max-microvolt = <1800000>; 517 regulator-min-microvolt = <1800000>; 518 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 519 }; 520 521 BUCK6 { 522 regulator-always-on; 523 regulator-boot-on; 524 regulator-max-microvolt = <1155000>; 525 regulator-min-microvolt = <1045000>; 526 regulator-name = "On-module +VDD_DDR (BUCK6)"; 527 }; 528 529 LDO1 { 530 regulator-always-on; 531 regulator-boot-on; 532 regulator-max-microvolt = <1950000>; 533 regulator-min-microvolt = <1650000>; 534 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 535 }; 536 537 LDO2 { 538 regulator-always-on; 539 regulator-boot-on; 540 regulator-max-microvolt = <1150000>; 541 regulator-min-microvolt = <800000>; 542 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 543 }; 544 545 LDO3 { 546 regulator-always-on; 547 regulator-boot-on; 548 regulator-max-microvolt = <1800000>; 549 regulator-min-microvolt = <1800000>; 550 regulator-name = "On-module +V1.8A (LDO3)"; 551 }; 552 553 LDO4 { 554 regulator-always-on; 555 regulator-boot-on; 556 regulator-max-microvolt = <3300000>; 557 regulator-min-microvolt = <3300000>; 558 regulator-name = "On-module +V3.3_ADC (LDO4)"; 559 }; 560 561 reg_vdd_sdio: LDO5 { 562 regulator-max-microvolt = <3300000>; 563 regulator-min-microvolt = <1800000>; 564 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 565 }; 566 }; 567 }; 568 569 rtc_i2c: rtc@32 { 570 compatible = "epson,rx8130"; 571 reg = <0x32>; 572 }; 573 574 /* On-module temperature sensor */ 575 hwmon_temp_module: sensor@48 { 576 compatible = "ti,tmp1075"; 577 reg = <0x48>; 578 vs-supply = <®_vdd_1v8>; 579 }; 580 581 adc@49 { 582 compatible = "ti,ads1015"; 583 reg = <0x49>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 587 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 588 channel@0 { 589 reg = <0>; 590 ti,datarate = <4>; 591 ti,gain = <2>; 592 }; 593 594 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 595 channel@1 { 596 reg = <1>; 597 ti,datarate = <4>; 598 ti,gain = <2>; 599 }; 600 601 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 602 channel@2 { 603 reg = <2>; 604 ti,datarate = <4>; 605 ti,gain = <2>; 606 }; 607 608 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 609 channel@3 { 610 reg = <3>; 611 ti,datarate = <4>; 612 ti,gain = <2>; 613 }; 614 615 /* Verdin I2C_1 ADC_4 */ 616 channel@4 { 617 reg = <4>; 618 ti,datarate = <4>; 619 ti,gain = <2>; 620 }; 621 622 /* Verdin I2C_1 ADC_3 */ 623 channel@5 { 624 reg = <5>; 625 ti,datarate = <4>; 626 ti,gain = <2>; 627 }; 628 629 /* Verdin I2C_1 ADC_2 */ 630 channel@6 { 631 reg = <6>; 632 ti,datarate = <4>; 633 ti,gain = <2>; 634 }; 635 636 /* Verdin I2C_1 ADC_1 */ 637 channel@7 { 638 reg = <7>; 639 ti,datarate = <4>; 640 ti,gain = <2>; 641 }; 642 }; 643 644 eeprom@50 { 645 compatible = "st,24c02"; 646 pagesize = <16>; 647 reg = <0x50>; 648 }; 649}; 650 651/* Verdin I2C_2_DSI */ 652&i2c2 { 653 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ 654 clock-frequency = <10000>; 655 pinctrl-names = "default", "gpio"; 656 pinctrl-0 = <&pinctrl_i2c2>; 657 pinctrl-1 = <&pinctrl_i2c2_gpio>; 658 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 659 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 660 661 atmel_mxt_ts_mezzanine: touch-mezzanine@4a { 662 compatible = "atmel,maxtouch"; 663 /* Verdin GPIO_3 (SODIMM 210) */ 664 interrupt-parent = <&gpio1>; 665 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 666 reg = <0x4a>; 667 /* Verdin GPIO_2 (SODIMM 208) */ 668 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 669 status = "disabled"; 670 }; 671}; 672 673/* Verdin I2C_4_CSI */ 674&i2c3 { 675 clock-frequency = <400000>; 676 pinctrl-names = "default", "gpio"; 677 pinctrl-0 = <&pinctrl_i2c3>; 678 pinctrl-1 = <&pinctrl_i2c3_gpio>; 679 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 680 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 681}; 682 683/* Verdin I2C_1 */ 684&i2c4 { 685 clock-frequency = <400000>; 686 pinctrl-names = "default", "gpio"; 687 pinctrl-0 = <&pinctrl_i2c4>; 688 pinctrl-1 = <&pinctrl_i2c4_gpio>; 689 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 690 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 691 692 gpio_expander_21: gpio-expander@21 { 693 compatible = "nxp,pcal6416"; 694 #gpio-cells = <2>; 695 gpio-controller; 696 reg = <0x21>; 697 vcc-supply = <®_3p3v>; 698 status = "disabled"; 699 }; 700 701 lvds_ti_sn65dsi84: bridge@2c { 702 compatible = "ti,sn65dsi84"; 703 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 704 /* Verdin GPIO_10_DSI (SODIMM 21) */ 705 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 708 reg = <0x2c>; 709 status = "disabled"; 710 }; 711 712 /* Current measurement into module VCC */ 713 hwmon: hwmon@40 { 714 compatible = "ti,ina219"; 715 reg = <0x40>; 716 shunt-resistor = <10000>; 717 status = "disabled"; 718 }; 719 720 hdmi_lontium_lt8912: hdmi@48 { 721 compatible = "lontium,lt8912b"; 722 pinctrl-names = "default"; 723 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 724 reg = <0x48>; 725 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 726 /* Verdin GPIO_10_DSI (SODIMM 21) */ 727 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 728 status = "disabled"; 729 }; 730 731 atmel_mxt_ts: touch@4a { 732 compatible = "atmel,maxtouch"; 733 /* 734 * Verdin GPIO_9_DSI 735 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 736 */ 737 interrupt-parent = <&gpio4>; 738 interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 741 reg = <0x4a>; 742 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 743 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 744 status = "disabled"; 745 }; 746 747 /* Temperature sensor on carrier board */ 748 hwmon_temp: sensor@4f { 749 compatible = "ti,tmp75c"; 750 reg = <0x4f>; 751 status = "disabled"; 752 }; 753 754 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 755 eeprom_display_adapter: eeprom@50 { 756 compatible = "st,24c02"; 757 pagesize = <16>; 758 reg = <0x50>; 759 status = "disabled"; 760 }; 761 762 /* EEPROM on carrier board */ 763 eeprom_carrier_board: eeprom@57 { 764 compatible = "st,24c02"; 765 pagesize = <16>; 766 reg = <0x57>; 767 status = "disabled"; 768 }; 769}; 770 771/* Verdin I2C_3_HDMI */ 772&i2c5 { 773 clock-frequency = <100000>; 774 pinctrl-names = "default", "gpio"; 775 pinctrl-0 = <&pinctrl_i2c5>; 776 pinctrl-1 = <&pinctrl_i2c5_gpio>; 777 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 778 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 779}; 780 781/* Verdin PCIE_1 */ 782&pcie { 783 pinctrl-names = "default"; 784 pinctrl-0 = <&pinctrl_pcie>; 785 /* PCIE_1_RESET# (SODIMM 244) */ 786 reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; 787}; 788 789&pcie_phy { 790 clocks = <&hsio_blk_ctrl>; 791 clock-names = "ref"; 792 fsl,clkreq-unsupported; 793 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 794}; 795 796/* Verdin PWM_1 */ 797&pwm1 { 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_pwm_1>; 800 #pwm-cells = <3>; 801}; 802 803/* Verdin PWM_2 */ 804&pwm2 { 805 pinctrl-names = "default"; 806 pinctrl-0 = <&pinctrl_pwm_2>; 807 #pwm-cells = <3>; 808}; 809 810/* Verdin PWM_3_DSI */ 811&pwm3 { 812 pinctrl-names = "default"; 813 pinctrl-0 = <&pinctrl_pwm_3>; 814 #pwm-cells = <3>; 815}; 816 817/* TODO: Verdin I2S_1 */ 818 819/* TODO: Verdin I2S_2 */ 820 821&snvs_pwrkey { 822 status = "okay"; 823}; 824 825/* Verdin UART_1 */ 826&uart1 { 827 pinctrl-names = "default"; 828 pinctrl-0 = <&pinctrl_uart1>; 829 uart-has-rtscts; 830}; 831 832/* Verdin UART_2 */ 833&uart2 { 834 pinctrl-names = "default"; 835 pinctrl-0 = <&pinctrl_uart2>; 836 uart-has-rtscts; 837}; 838 839/* Verdin UART_3, used as the Linux Console */ 840&uart3 { 841 pinctrl-names = "default"; 842 pinctrl-0 = <&pinctrl_uart3>; 843}; 844 845/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ 846&uart4 { 847 pinctrl-names = "default"; 848 pinctrl-0 = <&pinctrl_uart4>; 849}; 850 851/* Verdin USB_1 */ 852&usb3_0 { 853 fsl,disable-port-power-control; 854 fsl,over-current-active-low; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&pinctrl_usb_1_oc_n>; 857}; 858 859&usb_dwc3_0 { 860 /* dual role only, not full featured OTG */ 861 adp-disable; 862 dr_mode = "otg"; 863 hnp-disable; 864 maximum-speed = "high-speed"; 865 role-switch-default-mode = "peripheral"; 866 srp-disable; 867 usb-role-switch; 868 869 port { 870 usb3_dwc: endpoint { 871 remote-endpoint = <&usb_dr_connector>; 872 }; 873 }; 874}; 875 876/* Verdin USB_2 */ 877&usb3_1 { 878 fsl,disable-port-power-control; 879}; 880 881&usb3_phy1 { 882 vbus-supply = <®_usb2_vbus>; 883}; 884 885&usb_dwc3_1 { 886 dr_mode = "host"; 887}; 888 889/* Verdin SD_1 */ 890&usdhc2 { 891 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 892 assigned-clock-rates = <400000000>; 893 bus-width = <4>; 894 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 895 disable-wp; 896 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 897 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 898 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 899 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 900 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 901 vmmc-supply = <®_usdhc2_vmmc>; 902 vqmmc-supply = <®_vdd_sdio>; 903}; 904 905/* On-module eMMC */ 906&usdhc3 { 907 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 908 assigned-clock-rates = <400000000>; 909 bus-width = <8>; 910 non-removable; 911 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 912 pinctrl-0 = <&pinctrl_usdhc3>; 913 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 914 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 915 status = "okay"; 916}; 917 918&wdog1 { 919 fsl,ext-reset-output; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&pinctrl_wdog>; 922 status = "okay"; 923}; 924 925&iomuxc { 926 pinctrl_bt_uart: btuartgrp { 927 fsl,pins = 928 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>, 929 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>, 930 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>, 931 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>; 932 }; 933 934 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 935 fsl,pins = 936 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */ 937 }; 938 939 pinctrl_ecspi1: ecspi1grp { 940 fsl,pins = 941 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */ 942 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */ 943 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */ 944 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */ 945 }; 946 947 /* Connection On Board PHY */ 948 pinctrl_eqos: eqosgrp { 949 fsl,pins = 950 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, 951 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, 952 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, 953 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, 954 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, 955 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, 956 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, 957 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, 958 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, 959 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, 960 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, 961 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, 962 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, 963 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; 964 }; 965 966 /* ETH_INT# shared with TPM_INT# (usually N/A) */ 967 pinctrl_eth_tpm_int: ethtpmintgrp { 968 fsl,pins = 969 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>; 970 }; 971 972 /* Connection Carrier Board PHY ETH_2 */ 973 pinctrl_fec: fecgrp { 974 fsl,pins = 975 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 976 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 977 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 978 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 979 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 980 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 981 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 982 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 983 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */ 984 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */ 985 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */ 986 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */ 987 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */ 988 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */ 989 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */ 990 }; 991 992 pinctrl_fec_sleep: fecsleepgrp { 993 fsl,pins = 994 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 995 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 996 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 997 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 998 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 999 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 1000 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 1001 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 1002 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */ 1003 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */ 1004 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */ 1005 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */ 1006 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */ 1007 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */ 1008 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */ 1009 }; 1010 1011 pinctrl_flexcan1: flexcan1grp { 1012 fsl,pins = 1013 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */ 1014 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */ 1015 }; 1016 1017 pinctrl_flexcan2: flexcan2grp { 1018 fsl,pins = 1019 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */ 1020 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */ 1021 }; 1022 1023 pinctrl_flexspi0: flexspi0grp { 1024 fsl,pins = 1025 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */ 1026 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */ 1027 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */ 1028 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */ 1029 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */ 1030 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */ 1031 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */ 1032 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */ 1033 }; 1034 1035 pinctrl_gpio1: gpio1grp { 1036 fsl,pins = 1037 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */ 1038 }; 1039 1040 pinctrl_gpio2: gpio2grp { 1041 fsl,pins = 1042 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */ 1043 }; 1044 1045 pinctrl_gpio3: gpio3grp { 1046 fsl,pins = 1047 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */ 1048 }; 1049 1050 pinctrl_gpio4: gpio4grp { 1051 fsl,pins = 1052 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */ 1053 }; 1054 1055 pinctrl_gpio5: gpio5grp { 1056 fsl,pins = 1057 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */ 1058 }; 1059 1060 pinctrl_gpio6: gpio6grp { 1061 fsl,pins = 1062 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */ 1063 }; 1064 1065 pinctrl_gpio7: gpio7grp { 1066 fsl,pins = 1067 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */ 1068 }; 1069 1070 pinctrl_gpio8: gpio8grp { 1071 fsl,pins = 1072 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */ 1073 }; 1074 1075 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 1076 pinctrl_gpio_9_dsi: gpio9dsigrp { 1077 fsl,pins = 1078 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */ 1079 }; 1080 1081 /* Verdin GPIO_10_DSI */ 1082 pinctrl_gpio_10_dsi: gpio10dsigrp { 1083 fsl,pins = 1084 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */ 1085 }; 1086 1087 /* Non-wifi MSP usage only */ 1088 pinctrl_gpio_hog1: gpiohog1grp { 1089 fsl,pins = 1090 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */ 1091 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */ 1092 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */ 1093 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */ 1094 }; 1095 1096 /* USB_2_OC# */ 1097 pinctrl_gpio_hog2: gpiohog2grp { 1098 fsl,pins = 1099 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */ 1100 }; 1101 1102 pinctrl_gpio_hog3: gpiohog3grp { 1103 fsl,pins = 1104 /* CSI_1_MCLK */ 1105 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */ 1106 }; 1107 1108 /* Wifi usage only */ 1109 pinctrl_gpio_hog4: gpiohog4grp { 1110 fsl,pins = 1111 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */ 1112 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */ 1113 }; 1114 1115 pinctrl_gpio_keys: gpiokeysgrp { 1116 fsl,pins = 1117 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */ 1118 }; 1119 1120 pinctrl_hdmi_hog: hdmihoggrp { 1121 fsl,pins = 1122 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */ 1123 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */ 1124 }; 1125 1126 /* On-module I2C */ 1127 pinctrl_i2c1: i2c1grp { 1128 fsl,pins = 1129 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */ 1130 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */ 1131 }; 1132 1133 pinctrl_i2c1_gpio: i2c1gpiogrp { 1134 fsl,pins = 1135 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */ 1136 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */ 1137 }; 1138 1139 /* Verdin I2C_2_DSI */ 1140 pinctrl_i2c2: i2c2grp { 1141 fsl,pins = 1142 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */ 1143 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */ 1144 }; 1145 1146 pinctrl_i2c2_gpio: i2c2gpiogrp { 1147 fsl,pins = 1148 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */ 1149 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */ 1150 }; 1151 1152 /* Verdin I2C_4_CSI */ 1153 pinctrl_i2c3: i2c3grp { 1154 fsl,pins = 1155 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */ 1156 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */ 1157 }; 1158 1159 pinctrl_i2c3_gpio: i2c3gpiogrp { 1160 fsl,pins = 1161 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */ 1162 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */ 1163 }; 1164 1165 /* Verdin I2C_1 */ 1166 pinctrl_i2c4: i2c4grp { 1167 fsl,pins = 1168 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */ 1169 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */ 1170 }; 1171 1172 pinctrl_i2c4_gpio: i2c4gpiogrp { 1173 fsl,pins = 1174 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */ 1175 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */ 1176 }; 1177 1178 /* Verdin I2C_3_HDMI */ 1179 pinctrl_i2c5: i2c5grp { 1180 fsl,pins = 1181 <MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400001c6>, /* SODIMM 59 */ 1182 <MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400001c6>; /* SODIMM 57 */ 1183 }; 1184 1185 pinctrl_i2c5_gpio: i2c5gpiogrp { 1186 fsl,pins = 1187 <MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x400001c6>, /* SODIMM 59 */ 1188 <MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x400001c6>; /* SODIMM 57 */ 1189 }; 1190 1191 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1192 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1193 fsl,pins = 1194 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */ 1195 }; 1196 1197 /* Verdin I2S_2_D_OUT shared with SAI3 */ 1198 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1199 fsl,pins = 1200 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */ 1201 }; 1202 1203 pinctrl_pcie: pciegrp { 1204 fsl,pins = 1205 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */ 1206 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */ 1207 }; 1208 1209 pinctrl_pmic: pmicirqgrp { 1210 fsl,pins = 1211 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ 1212 }; 1213 1214 pinctrl_pwm_1: pwm1grp { 1215 fsl,pins = 1216 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */ 1217 }; 1218 1219 pinctrl_pwm_2: pwm2grp { 1220 fsl,pins = 1221 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */ 1222 }; 1223 1224 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */ 1225 pinctrl_pwm_3: pwm3grp { 1226 fsl,pins = 1227 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */ 1228 }; 1229 1230 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */ 1231 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp { 1232 fsl,pins = 1233 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */ 1234 }; 1235 1236 pinctrl_reg_eth: regethgrp { 1237 fsl,pins = 1238 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */ 1239 }; 1240 1241 pinctrl_sai1: sai1grp { 1242 fsl,pins = 1243 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */ 1244 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */ 1245 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */ 1246 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */ 1247 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */ 1248 }; 1249 1250 pinctrl_sai3: sai3grp { 1251 fsl,pins = 1252 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */ 1253 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */ 1254 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */ 1255 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */ 1256 }; 1257 1258 pinctrl_uart1: uart1grp { 1259 fsl,pins = 1260 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */ 1261 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */ 1262 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */ 1263 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */ 1264 }; 1265 1266 pinctrl_uart2: uart2grp { 1267 fsl,pins = 1268 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */ 1269 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */ 1270 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */ 1271 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */ 1272 }; 1273 1274 pinctrl_uart3: uart3grp { 1275 fsl,pins = 1276 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */ 1277 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */ 1278 }; 1279 1280 /* Non-wifi usage only */ 1281 pinctrl_uart4: uart4grp { 1282 fsl,pins = 1283 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */ 1284 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */ 1285 }; 1286 1287 pinctrl_usb1_vbus: usb1vbusgrp { 1288 fsl,pins = 1289 <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */ 1290 }; 1291 1292 /* USB_1_ID */ 1293 pinctrl_usb_1_id: usb1idgrp { 1294 fsl,pins = 1295 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */ 1296 }; 1297 1298 /* USB_1_OC# */ 1299 pinctrl_usb_1_oc_n: usb1ocngrp { 1300 fsl,pins = 1301 <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */ 1302 }; 1303 1304 pinctrl_usb2_vbus: usb2vbusgrp { 1305 fsl,pins = 1306 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */ 1307 }; 1308 1309 /* On-module Wi-Fi */ 1310 pinctrl_usdhc1: usdhc1grp { 1311 fsl,pins = 1312 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, 1313 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, 1314 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, 1315 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, 1316 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, 1317 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; 1318 }; 1319 1320 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1321 fsl,pins = 1322 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, 1323 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, 1324 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, 1325 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, 1326 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, 1327 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; 1328 }; 1329 1330 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1331 fsl,pins = 1332 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, 1333 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, 1334 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, 1335 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, 1336 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, 1337 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; 1338 }; 1339 1340 pinctrl_usdhc2_cd: usdhc2cdgrp { 1341 fsl,pins = 1342 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */ 1343 }; 1344 1345 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1346 fsl,pins = 1347 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */ 1348 }; 1349 1350 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1351 fsl,pins = 1352 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */ 1353 }; 1354 1355 pinctrl_usdhc2: usdhc2grp { 1356 fsl,pins = 1357 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */ 1358 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */ 1359 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */ 1360 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */ 1361 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */ 1362 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */ 1363 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */ 1364 }; 1365 1366 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1367 fsl,pins = 1368 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1369 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 1370 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 1371 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1372 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1373 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1374 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1375 }; 1376 1377 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1378 fsl,pins = 1379 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1380 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, 1381 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, 1382 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, 1383 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, 1384 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, 1385 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; 1386 }; 1387 1388 /* Avoid backfeeding with removed card power */ 1389 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1390 fsl,pins = 1391 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>, 1392 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, 1393 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, 1394 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, 1395 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, 1396 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, 1397 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; 1398 }; 1399 1400 pinctrl_usdhc3: usdhc3grp { 1401 fsl,pins = 1402 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1403 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, 1404 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, 1405 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, 1406 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, 1407 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, 1408 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, 1409 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, 1410 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, 1411 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, 1412 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, 1413 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; 1414 }; 1415 1416 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1417 fsl,pins = 1418 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1419 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, 1420 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 1421 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 1422 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 1423 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 1424 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 1425 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 1426 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 1427 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 1428 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 1429 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; 1430 }; 1431 1432 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1433 fsl,pins = 1434 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1435 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, 1436 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, 1437 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, 1438 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, 1439 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, 1440 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, 1441 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, 1442 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, 1443 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, 1444 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, 1445 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; 1446 }; 1447 1448 pinctrl_wdog: wdoggrp { 1449 fsl,pins = 1450 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */ 1451 }; 1452 1453 pinctrl_bluetooth_ctrl: bluetoothctrlgrp { 1454 fsl,pins = 1455 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */ 1456 }; 1457 1458 pinctrl_wifi_ctrl: wifictrlgrp { 1459 fsl,pins = 1460 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */ 1461 }; 1462 1463 pinctrl_wifi_i2s: wifii2sgrp { 1464 fsl,pins = 1465 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */ 1466 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */ 1467 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */ 1468 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */ 1469 }; 1470 1471 pinctrl_wifi_pwr_en: wifipwrengrp { 1472 fsl,pins = 1473 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */ 1474 }; 1475}; 1476