1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10/ { 11 aliases { 12 ethernet1 = ð1; 13 fsa1 = &fsa0; 14 fsa2 = &fsa1; 15 }; 16 17 led-controller { 18 compatible = "gpio-leds"; 19 pinctrl-names = "default"; 20 pinctrl-0 = <&pinctrl_gpio_leds>; 21 22 led-0 { 23 function = LED_FUNCTION_STATUS; 24 color = <LED_COLOR_ID_GREEN>; 25 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 26 default-state = "on"; 27 linux,default-trigger = "heartbeat"; 28 }; 29 30 led-1 { 31 function = LED_FUNCTION_STATUS; 32 color = <LED_COLOR_ID_RED>; 33 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 34 default-state = "off"; 35 }; 36 }; 37 38 pcie0_refclk: clock-pcie0 { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <100000000>; 42 }; 43 44 pps { 45 compatible = "pps-gpio"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_pps>; 48 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 49 }; 50 51 reg_usb2_vbus: regulator-usb2 { 52 compatible = "regulator-fixed"; 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_reg_usb2_en>; 55 regulator-name = "usb2_vbus"; 56 regulator-min-microvolt = <5000000>; 57 regulator-max-microvolt = <5000000>; 58 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; 59 enable-active-high; 60 }; 61 62 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 63 compatible = "regulator-fixed"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 66 regulator-name = "VDD_3V3_SD"; 67 regulator-max-microvolt = <3300000>; 68 regulator-min-microvolt = <3300000>; 69 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 70 enable-active-high; 71 off-on-delay-us = <12000>; 72 startup-delay-us = <100>; 73 }; 74}; 75 76&ecspi2 { 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_spi2>; 79 cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>, /* CS0 onboard TPM */ 80 <&gpio5 13 GPIO_ACTIVE_LOW>, /* CS1 off-board J32 SPI */ 81 <&gpio1 12 GPIO_ACTIVE_LOW>, /* CS3 off-board J52 FSA1 */ 82 <&gpio4 26 GPIO_ACTIVE_LOW>; /* CS2 off-board J51 FSA2 */ 83 status = "okay"; 84 85 tpm@0 { 86 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 87 reg = <0x0>; 88 spi-max-frequency = <10000000>; 89 }; 90}; 91 92&flexcan1 { 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_can1>; 95 status = "okay"; 96}; 97 98&flexcan2 { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_can2>; 101 status = "okay"; 102}; 103 104&gpio1 { 105 gpio-line-names = 106 "", "", "", "", 107 "", "", "", "", 108 "", "", "", "", 109 "", "fsa2_gpio1", "", "", 110 "", "", "", "", 111 "", "", "", "", 112 "", "", "", "", 113 "", "", "", ""; 114}; 115 116&gpio4 { 117 gpio-line-names = 118 "", "", "", "", 119 "", "", "", "", 120 "dio1", "fsa1_gpio2", "", "dio0", 121 "", "", "", "", 122 "", "", "", "", 123 "", "", "rs485_en", "rs485_term", 124 "fsa2_gpio2", "fsa1_gpio1", "", "rs485_half", 125 "", "", "", ""; 126}; 127 128&i2c2 { 129 accelerometer@19 { 130 compatible = "st,lis2de12"; 131 reg = <0x19>; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_accel>; 134 interrupt-parent = <&gpio4>; 135 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 136 st,drdy-int-pin = <1>; 137 }; 138 139 magnetometer@1e { 140 compatible = "st,lis2mdl"; 141 reg = <0x1e>; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_mag>; 144 interrupt-parent = <&gpio4>; 145 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 146 }; 147}; 148 149&i2c3 { 150 i2c-mux@70 { 151 compatible = "nxp,pca9548"; 152 reg = <0x70>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 /* J30 */ 157 fsa1: i2c@0 { 158 reg = <0>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_fsa2i2c>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 164 gpio@20 { 165 compatible = "nxp,pca9555"; 166 reg = <0x20>; 167 interrupt-parent = <&gpio4>; 168 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 169 interrupt-controller; 170 #interrupt-cells = <2>; 171 gpio-controller; 172 #gpio-cells = <2>; 173 }; 174 175 eeprom@54 { 176 compatible = "atmel,24c02"; 177 reg = <0x54>; 178 pagesize = <16>; 179 }; 180 181 eeprom@55 { 182 compatible = "atmel,24c02"; 183 reg = <0x55>; 184 pagesize = <16>; 185 }; 186 }; 187 188 /* J29 */ 189 fsa0: i2c@1 { 190 reg = <1>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_fsa1i2c>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 196 gpio@20 { 197 compatible = "nxp,pca9555"; 198 reg = <0x20>; 199 interrupt-parent = <&gpio4>; 200 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 201 interrupt-controller; 202 #interrupt-cells = <2>; 203 gpio-controller; 204 #gpio-cells = <2>; 205 }; 206 207 eeprom@54 { 208 compatible = "atmel,24c02"; 209 reg = <0x54>; 210 pagesize = <16>; 211 }; 212 213 eeprom@55 { 214 compatible = "atmel,24c02"; 215 reg = <0x55>; 216 pagesize = <16>; 217 }; 218 }; 219 220 /* J33 */ 221 i2c@2 { 222 reg = <2>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 }; 226 }; 227}; 228 229&pcie_phy { 230 clocks = <&pcie0_refclk>; 231 clock-names = "ref"; 232 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 233 fsl,clkreq-unsupported; 234 status = "okay"; 235}; 236 237&pcie { 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_pcie0>; 240 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 241 status = "okay"; 242 243 pcie@0,0 { 244 reg = <0x0000 0 0 0 0>; 245 device_type = "pci"; 246 #address-cells = <3>; 247 #size-cells = <2>; 248 ranges; 249 250 pcie@0,0 { 251 reg = <0x0000 0 0 0 0>; 252 device_type = "pci"; 253 #address-cells = <3>; 254 #size-cells = <2>; 255 ranges; 256 257 pcie@7,0 { 258 reg = <0x3800 0 0 0 0>; 259 device_type = "pci"; 260 #address-cells = <3>; 261 #size-cells = <2>; 262 ranges; 263 264 eth1: ethernet@0,0 { 265 reg = <0x0000 0 0 0 0>; 266 #address-cells = <3>; 267 #size-cells = <2>; 268 ranges; 269 local-mac-address = [00 00 00 00 00 00]; 270 }; 271 }; 272 }; 273 }; 274}; 275 276/* GPS */ 277&uart1 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_uart1>; 280 status = "okay"; 281}; 282 283/* RS232 */ 284&uart4 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_uart4>; 287 status = "okay"; 288}; 289 290/* USB1 - FSA1 */ 291&usb3_0 { 292 fsl,permanently-attached; 293 fsl,disable-port-power-control; 294 status = "okay"; 295}; 296 297&usb3_phy0 { 298 status = "okay"; 299}; 300 301&usb_dwc3_0 { 302 dr_mode = "host"; 303 status = "okay"; 304}; 305 306/* USB2 - USB3.0 Hub */ 307&usb3_1 { 308 fsl,permanently-attached; 309 fsl,disable-port-power-control; 310 status = "okay"; 311}; 312 313&usb3_phy1 { 314 vbus-supply = <®_usb2_vbus>; 315 status = "okay"; 316}; 317 318&usb_dwc3_1 { 319 dr_mode = "host"; 320 status = "okay"; 321}; 322 323/* SDIO 1.8V */ 324&usdhc1 { 325 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 326 pinctrl-0 = <&pinctrl_usdhc1>; 327 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 328 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 329 bus-width = <4>; 330 non-removable; 331 status = "okay"; 332}; 333 334/* microSD */ 335&usdhc2 { 336 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 337 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 338 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 339 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 340 cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; /* CD is active high */ 341 bus-width = <4>; 342 vmmc-supply = <®_usdhc2_vmmc>; 343 status = "okay"; 344}; 345 346&iomuxc { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_hog>; 349 350 pinctrl_hog: hoggrp { 351 fsl,pins = < 352 MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ 353 MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ 354 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ 355 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ 356 MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ 357 >; 358 }; 359 360 pinctrl_accel: accelgrp { 361 fsl,pins = < 362 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ# */ 363 >; 364 }; 365 366 pinctrl_can1: can1grp { 367 fsl,pins = < 368 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 369 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 370 >; 371 }; 372 373 pinctrl_can2: can2grp { 374 fsl,pins = < 375 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 376 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 377 >; 378 }; 379 380 pinctrl_gpio_leds: gpioledgrp { 381 fsl,pins = < 382 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ 383 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ 384 >; 385 }; 386 387 pinctrl_fsa1i2c: fsa1i2cgrp { 388 fsl,pins = < 389 MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1d0 /* FSA1_ALERT# */ 390 MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x400001d0 /* FSA1_GPIO1 */ 391 MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x400001d0 /* FSA1_GPIO2 */ 392 >; 393 }; 394 395 pinctrl_fsa2i2c: fsa2i2cgrp { 396 fsl,pins = < 397 MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x1d0 /* FSA2_ALERT# */ 398 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x400001d0 /* FSA2_GPIO1 */ 399 MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x400001d0 /* FSA2_GPIO2 */ 400 >; 401 }; 402 403 pinctrl_mag: maggrp { 404 fsl,pins = < 405 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x140 /* IRQ# */ 406 >; 407 }; 408 409 pinctrl_pcie0: pcie0grp { 410 fsl,pins = < 411 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 /* PERST# */ 412 >; 413 }; 414 415 pinctrl_pps: ppsgrp { 416 fsl,pins = < 417 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 418 >; 419 }; 420 421 pinctrl_reg_usb2_en: regusb2grp { 422 fsl,pins = < 423 MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ 424 >; 425 }; 426 427 pinctrl_spi2: spi2grp { 428 fsl,pins = < 429 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0xd0 430 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0xd0 431 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0xd0 432 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 /* J32_CS */ 433 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 /* TPM_CS */ 434 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 /* FSA1_CS */ 435 MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x140 /* FSA2_CS */ 436 >; 437 }; 438 439 pinctrl_uart1: uart1grp { 440 fsl,pins = < 441 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 442 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 443 >; 444 }; 445 446 pinctrl_uart4: uart4grp { 447 fsl,pins = < 448 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 449 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 450 >; 451 }; 452 453 pinctrl_usdhc1: usdhc1grp { 454 fsl,pins = < 455 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 456 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 457 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 458 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 459 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 460 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 461 >; 462 }; 463 464 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 465 fsl,pins = < 466 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 467 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 468 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 469 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 470 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 471 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 472 >; 473 }; 474 475 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 476 fsl,pins = < 477 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 478 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 479 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 480 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 481 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 482 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 483 >; 484 }; 485 486 pinctrl_usdhc2: usdhc2grp { 487 fsl,pins = < 488 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 489 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 490 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 491 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 492 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 493 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 494 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 495 >; 496 }; 497 498 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 499 fsl,pins = < 500 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 501 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 502 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 503 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 504 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 505 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 506 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 507 >; 508 }; 509 510 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 511 fsl,pins = < 512 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 513 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 514 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 515 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 516 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 517 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 518 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 519 >; 520 }; 521 522 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 523 fsl,pins = < 524 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1d0 525 >; 526 }; 527 528 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 529 fsl,pins = < 530 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 531 >; 532 }; 533}; 534