1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10/ { 11 led-controller { 12 compatible = "gpio-leds"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_gpio_leds>; 15 16 led-0 { 17 function = LED_FUNCTION_STATUS; 18 color = <LED_COLOR_ID_GREEN>; 19 gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; 20 default-state = "on"; 21 linux,default-trigger = "heartbeat"; 22 }; 23 24 led-1 { 25 function = LED_FUNCTION_STATUS; 26 color = <LED_COLOR_ID_RED>; 27 gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; 28 default-state = "off"; 29 }; 30 }; 31 32 pcie0_refclk: pcie0-refclk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <100000000>; 36 }; 37 38 pps { 39 compatible = "pps-gpio"; 40 pinctrl-names = "default"; 41 pinctrl-0 = <&pinctrl_pps>; 42 gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; 43 status = "okay"; 44 }; 45 46 reg_usb2_vbus: regulator-usb2-vbus { 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_reg_usb2_en>; 49 compatible = "regulator-fixed"; 50 regulator-name = "usb2_vbus"; 51 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 regulator-min-microvolt = <5000000>; 54 regulator-max-microvolt = <5000000>; 55 }; 56 57 reg_usdhc2_vmmc: regulator-usdhc2 { 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 60 compatible = "regulator-fixed"; 61 regulator-name = "SD2_3P3V"; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 65 enable-active-high; 66 }; 67}; 68 69/* off-board header */ 70&ecspi2 { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_spi2>; 73 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 74 status = "okay"; 75}; 76 77&gpio4 { 78 gpio-line-names = 79 "", "", "", "", 80 "", "", "", "", 81 "", "", "", "", 82 "", "gpioa", "", "", 83 "", "", "", "", 84 "", "", "", "", 85 "", "", "", "", 86 "", "", "", ""; 87}; 88 89&gpio4 { 90 gpio-line-names = 91 "", "gpiod", "", "", 92 "gpiob", "gpioc", "", "", 93 "", "", "", "", 94 "", "", "", "", 95 "", "", "", "", 96 "", "", "", "", 97 "", "", "pci_usb_sel", "", 98 "pci_wdis#", "", "", ""; 99}; 100 101&i2c2 { 102 clock-frequency = <400000>; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_i2c2>; 105 status = "okay"; 106 107 accelerometer@19 { 108 compatible = "st,lis2de12"; 109 reg = <0x19>; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_accel>; 112 interrupt-parent = <&gpio5>; 113 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 114 st,drdy-int-pin = <1>; 115 }; 116 117 eeprom@52 { 118 compatible = "atmel,24c32"; 119 reg = <0x52>; 120 pagesize = <32>; 121 }; 122}; 123 124/* off-board header */ 125&i2c3 { 126 clock-frequency = <400000>; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_i2c3>; 129 status = "okay"; 130}; 131 132&pcie_phy { 133 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 134 fsl,clkreq-unsupported; 135 clocks = <&pcie0_refclk>; 136 clock-names = "ref"; 137 status = "okay"; 138}; 139 140&pcie { 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_pcie0>; 143 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 144 status = "okay"; 145}; 146 147/* GPS */ 148&uart1 { 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_uart1>; 151 status = "okay"; 152}; 153 154/* USB1 - Type C front panel SINK port J14 */ 155&usb3_0 { 156 status = "okay"; 157}; 158 159&usb3_phy0 { 160 status = "okay"; 161}; 162 163&usb_dwc3_0 { 164 dr_mode = "peripheral"; 165 status = "okay"; 166}; 167 168/* USB2 4-port USB3.0 HUB: 169 * P1 - USBC connector (host only) 170 * P2 - USB2 test connector 171 * P3 - miniPCIe full card 172 * P4 - miniPCIe half card 173 */ 174&usb3_phy1 { 175 vbus-supply = <®_usb2_vbus>; 176 status = "okay"; 177}; 178 179&usb3_1 { 180 fsl,permanently-attached; 181 fsl,disable-port-power-control; 182 status = "okay"; 183}; 184 185&usb_dwc3_1 { 186 dr_mode = "host"; 187 status = "okay"; 188}; 189 190/* microSD */ 191&usdhc2 { 192 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 193 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 194 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 195 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 196 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 197 vmmc-supply = <®_usdhc2_vmmc>; 198 bus-width = <4>; 199 status = "okay"; 200}; 201 202&iomuxc { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_hog>; 205 206 pinctrl_hog: hoggrp { 207 fsl,pins = < 208 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ 209 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ 210 MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ 211 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ 212 MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ 213 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ 214 >; 215 }; 216 217 pinctrl_accel: accelgrp { 218 fsl,pins = < 219 MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x159 220 >; 221 }; 222 223 pinctrl_gpio_leds: gpioledgrp { 224 fsl,pins = < 225 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ 226 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ 227 >; 228 }; 229 230 pinctrl_i2c2: i2c2grp { 231 fsl,pins = < 232 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 233 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 234 >; 235 }; 236 237 pinctrl_i2c3: i2c3grp { 238 fsl,pins = < 239 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 240 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 241 >; 242 }; 243 244 pinctrl_pcie0: pciegrp { 245 fsl,pins = < 246 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 247 >; 248 }; 249 250 pinctrl_pps: ppsgrp { 251 fsl,pins = < 252 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 253 >; 254 }; 255 256 pinctrl_reg_usb2_en: regusb2grp { 257 fsl,pins = < 258 MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ 259 >; 260 }; 261 262 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 263 fsl,pins = < 264 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 265 >; 266 }; 267 268 pinctrl_spi2: spi2grp { 269 fsl,pins = < 270 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 271 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 272 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 273 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 274 >; 275 }; 276 277 pinctrl_uart1: uart1grp { 278 fsl,pins = < 279 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 280 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 281 >; 282 }; 283 284 pinctrl_usdhc2: usdhc2grp { 285 fsl,pins = < 286 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 287 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 288 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 289 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 290 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 291 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 292 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 293 >; 294 }; 295 296 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 297 fsl,pins = < 298 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 299 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 300 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 301 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 302 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 303 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 304 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 305 >; 306 }; 307 308 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 309 fsl,pins = < 310 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 311 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 312 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 313 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 314 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 315 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 316 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 317 >; 318 }; 319 320 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 321 fsl,pins = < 322 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 323 >; 324 }; 325}; 326